Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.00TH8507)
DOI: 10.1109/isapm.2000.869248
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A novel epoxy encapsulant for CSP (μBGA(R))-new hydrophobic epoxy elastomer

Abstract: Due to an increasing demand for smaller and higher density packages, Tessera developed pBGA@ technology as a cost-effective solution for chip-size packaging. Many companies including Intel, 3M, Samsung, Amkor, etc. have licensed the technology since 1995. As a current, leading technology for Chip Scale Packaging (CSP), a pBGA@ package typically has a compliant layer between the die and the flex interposer to eliminate strain on solder balls by thermal mismatch of the die and printed wire board (PWB). Historica… Show more

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“…For this reason, various WLPs are created to enhance the reliability. Tessera Inc. developed the well-known BGA package through the creative concept of a stress buffer layer between the bump array and the silicon, to release the thermal stress [10]. Flip Chip International made use of both two dielectric layers, one of polymer and one metallic layer to redistribute the input/output (I/O) pads of the UltraCSP WLP, and the lager solder ball is also used to increase its reliability [11].…”
Section: Introductionmentioning
confidence: 99%
“…For this reason, various WLPs are created to enhance the reliability. Tessera Inc. developed the well-known BGA package through the creative concept of a stress buffer layer between the bump array and the silicon, to release the thermal stress [10]. Flip Chip International made use of both two dielectric layers, one of polymer and one metallic layer to redistribute the input/output (I/O) pads of the UltraCSP WLP, and the lager solder ball is also used to increase its reliability [11].…”
Section: Introductionmentioning
confidence: 99%
“…For this reason, various WLPs are created to enhance the reliability. Tessera Inc. developed the well-known /1 BGA package through the creative concept of a stress buffer layer between the bump array and the silicon, to release the thermal stress [9]. Kulicke & Soffa Inc. made use of both two dielectric layers, one of polymer and one metallic layer to redistribute the 110 pads of the UltraCSP WLP, and the lager solder ball is also used to increase its reliability [IO].…”
Section: Introductionmentioning
confidence: 99%