A novel dynamic memory cell with internal voltage gain

Luk, W.K.; Dennard, R.H.

doi:10.1109/jssc.2004.842854

Cited by 32 publications

(24 citation statements)

References 2 publications

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“…A preliminary analysis of gated-diode operation in planar single-gate technology is available in [3], [4], [5]. In this section, we develop an augmented model of internal voltage gain [3] to aid the design of fin gated-diodes for voltageboosting, show that it matches well with device simulation in Section V and extend it to zero-suppression using p-type gated-diodes in Section VII.…”

Section: Operating Principle Of the Gated-diodementioning

confidence: 88%

“…1) can be implemented in bulk silicon either by shorting the source and drain of a FET or fabricating a 'partial' FET with a source and no drain [3], to form a two-terminal device. The nonlinear C-V characteristic of T G can be leveraged to obtain internal voltage gain in gain memory cells like 2T/3T1D DRAMs (Fig.…”

Section: A Internal Voltage Gainmentioning

confidence: 99%

“…Also, high-speed, lowvoltage operation is difficult due to a low signal-to-noise ratio. Gain memory cells like the bulk 2T/3T1D DRAMs described in [3] (Fig. 1) score over 1T1C cells due to their non-destructive read-out feature, low read latency and high signal-to-noise ratio even under low voltage operation.…”

Section: Gated-diode Finfet Dram Cellsmentioning

confidence: 99%

“…Increased scaling has placed considerable stress on SRAM technology due to the effects of process variations on performance, stability and standby leakage power consumption. In order to circumvent the SRAM scaling/variability problem, researchers have considered replacing bulk SRAM with 2T/3T1D bulk DRAM [2], [3], or switching to a multi-gate implementation, such as FinFET SRAM [8], [9], [10]. 3T1D DRAM was shown to meet the performance requirements of an L1 cache memory in the temporal window of repeated accesses/writes, thereby obviating the need for a static memory, in [2].…”

Section: Introductionmentioning

confidence: 99%

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Pragmatic design of gated-diode FinFET DRAMs

Bhoj

Jha

2009

2009 IEEE International Conference on Computer Design

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Abstract-Scaling bulk CMOS SRAM technology for onchip caches beyond the 22nm node is questionable, on account of high leakage power consumption, performance degradation, and instability due to process variations. Recently, two/three transistor one gated-diode (2T/3T1D) DRAMs were proposed as alternatives to address the SRAM variability problem, with an emphasis on high-activity embedded cache applications. They are highly competitive with an SRAM in terms of performance, while having a smaller power and area footprint at lower technology nodes. The current evolutionary trend in transistor structures is toward an era of multi-gate devices, which makes it necessary to identify design issues and advantages of gated-diode DRAMs implemented in a multi-gate technology.In this work, we address gated-diode DRAM design in FinFET technology using mixed-mode 2D-device simulations. We revisit the model of internal voltage gain in bulk gated-diodes and extend it to provide quantitative insight into designing Fin gated-diodes, i.e., gated-diodes in FinFET technology. To this effect, we propose FinFET variants of the bulk gated-diode configuration and identify parameters that are critical to enhancing the retention time and read current in 2T/3T1D FinFET DRAMs. Additionally, we show the superiority of 2T1D FinFET DRAM over 6T FinFET SRAM having pass-gate feedback (6T PGFB) and 2T1D bulk DRAM under the effect of variations using a quasi-Monte Carlo method implemented in FinE, an environment we have developed for double-gate circuit design that integrates Sentaurus TCAD from Synopsys with the Spice3-UFDG double-gate compact model from University of Florida under a single framework. Finally, we present a new tunable threshold gated-diode FinFET amplifier which uses an n-type gated-diode for voltage-boosting, along with a p-type gated-diode for zero-suppression.

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Section: Operating Principle Of the Gated-diodementioning

confidence: 88%

Section: A Internal Voltage Gainmentioning

confidence: 99%

Section: Gated-diode Finfet Dram Cellsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Pragmatic design of gated-diode FinFET DRAMs

Bhoj

Jha

2009

2009 IEEE International Conference on Computer Design

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“…The gain memory cells are made of logic devices allowing them to be built in a standard CMOS process [1,2]. Their bit data are stored on parasitic capacitances of the cell itself.…”

Section: Introductionmentioning

confidence: 99%

A Logic-compatible Embedded DRAM Utilizing Common-body Toggled Capacitive Cross-talk

Cheng¹,

Das²,

Chung³

2016

JSTS:Journal of Semiconductor Technology and Science

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P‐channel logic 2 T eDRAM macro with high retention bit architecture

Manisankar

Chung

2018

Circuit Theory & Apps

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Summary This study presents a novel approach which enhances the data retention capability of PMOS gain cell based embedded DRAM. The proposed circuit technique utilizes a parasitic capacitance between the cell storage node and the common n‐well body. During the write operation, an up‐down voltage transition to the n‐well increases the cell storage retention time without using any optional devices. It also results in much high immunity against the write “1” disturbance. Measured and simulated results from an 8192‐wordx8‐bit eDRAM macro implemented in a 0.13‐μm generic CMOS process exhibit 58% increased retention time and approximately 3.6 times stronger write disturbance immunity over the conventional design.

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A novel dynamic memory cell with internal voltage gain

Cited by 32 publications

References 2 publications

Pragmatic design of gated-diode FinFET DRAMs

Pragmatic design of gated-diode FinFET DRAMs

A Logic-compatible Embedded DRAM Utilizing Common-body Toggled Capacitive Cross-talk

P‐channel logic 2 T eDRAM macro with high retention bit architecture

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