A novel dual-channel 3D NAND flash featuring both N-channel and P-channel NAND characteristics for bit-alterable Flash memory and a new opportunity in sensing the stored charge in the WL space

Lue, Hang-Ting; Du, Pei-Ying; Chen, Wei‐Chen; Yeh, Teng-Hao; Chang, Kuo-Ping; Hsiao, Yi‐Hsuan; Shih, Yung‐Feng; Hung, Chun-Hsiung; Lu, Chih‐Yuan

doi:10.1109/iedm.2013.6724555

Cited by 17 publications

(3 citation statements)

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“…When the number of stored electrons reaches statistical limits, continued scaling is more and more challenging for charge-based non-volatile memory (NVM) devices 1 . As a solution, 3D vertical NAND technology is emerging, which achieves ultra-high bit density by stacking memory layers 2 3 . Recently, resistive random access memory (RRAM) has shown excellent advantages in feature size scaling and speed 4 5 6 , and is believed as one of the most promising candidates for next-generation NVM 7 8 9 10 .…”

mentioning

confidence: 99%

Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory

Bai

et al. 2014

Sci Rep

110

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Three-dimensional (3D) integration and multi-level cell (MLC) are two attractive technologies to achieve ultra-high density for mass storage applications. In this work, a three-layer 3D vertical AlOδ/Ta2O5-x/TaOy resistive random access memories were fabricated and characterized. The vertical cells in three layers show good uniformity and high performance (e.g. >1000X HRS/LRS windows, >1010 endurance cycles, >104 s retention times at 125°C). Meanwhile, four level MLC is demonstrated with two operation strategies, current controlled scheme (CCS) and voltage controlled scheme (VCS). The switching mechanism of 3D vertical RRAM cells is studied based on temperature-dependent transport characteristics. Furthermore, the applicability of CCS and VCS in 3D vertical RRAM array is compared using resistor network circuit simulation.

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confidence: 99%

Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory

Bai

et al. 2014

Sci Rep

110

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“…The pass bias scheme is required in this cell string having a poly-Si channel to utilize the PF, since the diffusion length of holes is reduced by 100 times in this paper due to the reduced carrier mobility and lifetime. The conventional pass bias scheme [18], as shown in Fig. 2(c), cannot guarantee the super-steep SS in our diode-type cell string, because the carrier (hole) recombination can take place before triggering the PF.…”

Section: A Read Operation Scheme and I B L -V Cg Characteristics Of mentioning

confidence: 98%

Diode-Type NAND Flash Memory Cell String Having Super-Steep Switching Slope Based on Positive Feedback

Joe

Kang

Choi

et al. 2016

IEEE Trans. Electron Devices

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A positive feedback (PF) mechanism was adopted for the first time in the cell string of a 3-D NAND flash memory where n + and p + regions are formed on both ends of the string to implement a diode-type cell string. The body consists of a tubetype poly-Si channel. To generate the PF in the channel during a read operation, a new read operation scheme is proposed. In this paper, the simulator was calibrated in terms of trap density ( D it ) of a poly-Si channel extracted from fabricated 3-D NAND flash memory cells. By utilizing the PF, a NAND flash memory cell in a cell string has a steep subthreshold swing of <1 mV/decade.

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“…As one of the most promising emerging non-volatile memory (NVM) devices, oxide-based resistive switching memory (RRAM) has attracted significant interests due to the super endurance, fast switching speed, low power consumption and good CMOS compatibility 1 2 3 4 5 6 7 . On the other hand, current flash technology also found a way to overcome its scaling limit by adopting three dimensional (3D) structure to achieve high density 8 9 . The 3D RRAM approach, which combines the advantages of excellent electrical performances in RRAM cell and high density of 3D configuration, becomes a very attractive candidate for next generation high density NVM applications 10 11 12 .…”

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confidence: 99%

Stacked 3D RRAM Array with Graphene/CNT as Edge Electrodes

Bai

Wang

et al. 2015

Sci Rep

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There are two critical challenges which determine the array density of 3D RRAM: 1) the scaling limit in both horizontal and vertical directions; 2) the integration of selector devices in 3D structure. In this work, we present a novel 3D RRAM structure using low-dimensional materials, including 2D graphene and 1D carbon nanotube (CNT), as the edge electrodes. A two-layer 3D RRAM with monolayer graphene as edge electrode is demonstrated. The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale. Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized. Furthermore, the discussion of high array density potential is presented.

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A novel dual-channel 3D NAND flash featuring both N-channel and P-channel NAND characteristics for bit-alterable Flash memory and a new opportunity in sensing the stored charge in the WL space

Cited by 17 publications

References 0 publications

Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory

Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory

Diode-Type NAND Flash Memory Cell String Having Super-Steep Switching Slope Based on Positive Feedback

Stacked 3D RRAM Array with Graphene/CNT as Edge Electrodes

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