A novel double-trapping BE-SONOS charge-trapping NAND flash device to overcome the erase saturation without using curvature-induced field enhancement effect or high-K (HK)/metal gate (MG) materials

Abstract

Erase saturation issue is a fundamental challenge for SONOStype charge-trapping NAND Flash devices. Nowadays the most popular way to solve this issue is to pursue either curvature-induced field enhancement effect in the nano-wire SONOS device, or HK/MG to suppress the gate injection. However, both approaches have its drawback and reliability challenges. In this work, we propose a completely different approach that utilizes a double-trapping (or double storage) layer in a barrier engineered (BE) SONOS device to overcome the erase saturation ideally. A second nitride trapping layer (N3) is stacked on top of the first blocking oxide (O3) and 1st trapping layer (N2) of the original BE-SONOS device. Both theoretical model and experimental measured results indicate that when N3 stores sufficient electron charge it can greatly suppress gate injection, allowing continuous hole injection into N2 that gives a very deep erased Vt ~ -6V. A fully-integrated 3D Vertical Gate (VG) NAND Flash test chip using this novel device has been fabricated which demonstrates excellent MLC operation window and reliability. The flat and planar topology of this double-trapping BE-SONOS device enables minimal design rule of 3D NAND Flash array and possesses superb read disturb immunity.

3D NAND Flash Based on Planar Cells

“…For example, the use of a combination of a Hi-K metal gate and thicker oxide to improve both retention and erasing has been studied. Barrier Engineered (BE-SONOS) approach to CT [7][8][9][10][11][12] consists of replacing the trapping oxide with a stack of layers, O/N/O/N/O, so as to modify the band structure of the oxide in order to reduce the unwanted drawbacks of the structure ( Figure 5). …”

“…CT cells have already been proposed as a suitable candidate to replace FGs below 40 nm but finally have not been used in 2D NAND [7][8][9][10][11][12].…”

3D VG-Type NAND Flash Memories

“…Vertical Channel devices, which usually have a gate-all-around structure, can benefit from the Electric Field Enhancement (FE) due to the curvature effect which reduces the electric field through the gate, thus mitigating the electrons injection from the poly gate. However, FE method has several drawbacks and imposes limitations on the cell size [32,23]. Another way to reduce gate injection would be through the use of Hi-K material which can minimize the electric field in the oxide.…”

“…BE-SONOS devices allow avoiding the complication and drawbacks of FE or the use of Hi-K materials. In 3D-VG NAND, further engineering of the BE-SONOS structure is possible, thanks to the planar and very uniform structure [23]. In Fig.…”