A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Abstract

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.Index Terms-Delamination layer, memory, wafer level chip scale packaging (WLCSP).

Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

“…Design and fabrication of a foldable 3D silicon based package for solid state lighting applications R Sokolovskij 1,2,4 , P Liu 1,4 , H W van Zeijl 1 , B Mimoun 1,3 and G Q Zhang 1 is already successfully applied in chip-scale (CP) CMOS packages, to insulate dies and form fan-outs from peripheral bondpads to area-arrays for flip-chip mounting with larger pitch [5]. Benefits of CP-WLP include not only cost reduction, but also minimized footprint, higher vibration and shock resilience and possibility to perform on-wafer packaged testing [6].…”