A Novel Design of Low Power &amp; High Speed FinFET Based Binary and Ternary SRAM and 4*4 SRAM Array

Shylashree, N.; Amulya, M. S.; Disha, Gulur R.; Praveena, N.; Verma, Vijay Kumar; Muthumanickam, S.; Kannagi, V.; Sivachandar, K.; Nath, Vijay

doi:10.1080/03772063.2023.2207549

IETE Journal of Research

2023

DOI: 10.1080/03772063.2023.2207549

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A Novel Design of Low Power & High Speed FinFET Based Binary and Ternary SRAM and 4*4 SRAM Array

N. Shylashree,

M. S. Amulya,

Gulur R. Disha

et al.

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2024

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“…The average power consumption of the proposed CNTFET based TSRAM is lower compared to TSRAM cells designed in other well-established technologies at 0.9 V supply. The power consumption of TSRAM cell in fin field effect transistor (FinFET) technology is 5.38 mW[60], and 0.805 mW[61], in graphene nanoribbon field effect transistor (GNRFET) technology it is 1.33 mW[62]. The various attributes of state of art of various TSRAM cells is summarized in table 3.…”

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Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

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In this paper, a carbon nanotube field-effect transistor (CNTFET) based low power and robust ternary SRAM (TSRAM) cell with enhanced static noise margin (SNM) has been proposed. The proposed cell uses a low-power cell core and a stack of 2 CNTFETs to discharge the read bit line (RBL) to ground, unlike the previous SRAM designs which use read buffers or transmission gates (TG) to alter the voltage levels on the RBL. The proposed TSRAM cell has been simulated relentlessly, using the Stanford 32 nm CNTFET technology mode file with Synopsis HSPICE tool under various operating conditions. Unlike other designs, the cross-coupled ternary inverters used as the cell core in the proposed TSRAM show higher gain and steep curves in the transition region mitigating the static power of the cell. The simulation results exhibit improvements in performance parameters like power consumption, energy, noise margins, and reliability. At 0.9 V supply voltage, the proposed TSRAM cell offers 52.44% and 43.17% reduction in write and read static power, a PDP reduction of 35.29% in comparison, and a 36.36% improvement in SNM compared to best designs under investigation. Also, the proposed TSRAM design shows higher robustness compared to other designs.

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mentioning

confidence: 99%

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

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A Novel Design of Low Power & High Speed FinFET Based Binary and Ternary SRAM and 4*4 SRAM Array

Cited by 1 publication

References 26 publications

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

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