A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs

Bolchini, Cristiana; Miele, Antonio; Sandionigi, Chiara

doi:10.1109/tc.2010.281

Cited by 73 publications

(71 citation statements)

References 23 publications

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“…For a set of benchmark circuits, an average MTTR reduction of 30% was achieved. A methodology with a similar aim is presented in [Bolchini et al 2011]. The authors partition a circuit design and apply a specific redundancy scheme (like DWC or TMR) to each partition.…”

Section: Methodology Attributesmentioning

confidence: 99%

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Siegle

Vladimirova

Ilstad³

et al. 2015

ACM Comput. Surv.

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The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.

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Section: Methodology Attributesmentioning

confidence: 99%

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Siegle

Vladimirova

Ilstad³

et al. 2015

ACM Comput. Surv.

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“…• definition of a design methodology for the realization of systems able to mitigate SE effects in the programmable part of SoPC platforms, by exploiting both classical and new fault detection and tolerance techniques, together with reconfiguration features [27], [28], [29]; and • definition of a suitable controller architecture for the management of the reconfiguration phase used to recover from the detected soft errors [30], [31].…”

Section: Design Methodologies For Implementing Hardened Systems Onmentioning

confidence: 99%

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Bolchini

Miele

Sandionigi

et al. 2012

2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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This paper reports the main contribution of a project devoted to the definition of techniques to design and evaluate fault tolerant systems implemented using the SoPC paradigm, suitable for mission- and safety-critical application environments. In particular, the effort of the five involved research units has been devoted to address some of the main issues related to the specific technological aspects introduced by these flexible platforms. The overall target of the research is the development of a design methodology for highly reliable systems realized on reconfigurable platforms based on a System-on-Programmable Chip (SoPC)

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“…And a different scrubber may perform ID preventive scrubbing, on a device-oriented basis and with a variable readback rate. 1D/2D reconfiguration was also considered in [34] for blockbased error mitigation.…”

Section: Id Vs 2d Scrubbingmentioning

confidence: 99%

“…As a final consideration, reliability can be improved at design time by analyzing the most sensitive parts of the design and performing a reliability-aware place and route of the design in the FPGA [47], [34].…”

Section: A Reliability and Availabilitymentioning

confidence: 99%

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

Herrera-Alzu

López‐Vallejo

2013

IEEE Trans. Nucl. Sci.

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Abstract-SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers.

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A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs

Cited by 73 publications

References 23 publications

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

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