A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power

Karimi, Ahmad; Rezai, Abdalhossein; Hajhashemkhani, Mohammad Mahdi

doi:10.1016/j.vlsi.2017.09.002

Cited by 24 publications

(15 citation statements)

References 31 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As we have proposed SRs out of DFF, we have taken similar low-power DFFs for building register designs. They are named as follows: transmission gate SR developed from a conventional transmission gate FF (TGSR) (Zhang et al , 2011); topologically compressed SR made out of topologically compressed FF (TCSR) (Kawai et al , 2014); logic structure reduction technique SR developed from logic structure reduction technique FF (LRSR) (Lin et al , 2017); SR made from a dynamic FF designed by author Gago (GagoSR) (Gago et al , 1993); pulse-triggered SR from pulse-triggered FF (PTSR) (Karimi et al , 2018); lector-based clock gating SR developed from LBCG FF (LBCG-SR) (Bhattacharjee and Majumder, 2018); scan SR developed from Scan FF (SC-SR) (Razmdideh et al , 2015); 18 transistor SRs made from 18TFF (18TSR) (Cai et al , 2018); and implicit pulse-triggered FF with clock gating and pull-up control scheme SR developed from IP-CGPC FF (IP-CGPCSR) (Geng et al , 2016). …”

Section: Resultsmentioning

confidence: 99%

Power and area-efficient register designs involving EHO algorithm

Sabu

Batri

2020

View full text Add to dashboard Cite

Purpose This paper aims to design three low-power and area-efficient serial input parallel output (SIPO) register designs, namely, transistor count reduction technique shift register (TCRSR), series stacking in TCR shift register (S-TCRSR) and forced stacking of transistor in TCR shift register (FST in TCRSR). Shift registers (SR) are the basic building blocks of all types of digital applications. The performance of all the designs has been improved through one of the metaheuristic algorithms named elephant herding optimization (EHO) algorithm and hence suited for low-power very large scale integration (VLSI) applications. It is for the first time that the EHO algorithm is implemented in memory elements. Design/methodology/approach The registers together with clock network consume 18-36 percentage of the total power consumption of a microprocessor. The proposed designs are implemented using low-power and high-performance double edge-triggered D flip-flops with least count of clocked transistors involving transmission gate. The second and third register designs are developed from the modified version of the first one employing series and forced stacking, thereby reducing static power because of sub-threshold leakage current. The performance parameters such as power-delay-product (PDP) and leakage power are further optimized using the EHO algorithm. A greater reduction in power is achieved in all the designs by utilizing the EHO algorithm. Findings All the designs are simulated at a supply voltage of 1 V/500 MHz when the input switching activity is 25 percentage in Cadence Virtuoso using 45 nm CMOS technology. Nine recently proposed SR designs are simulated in the same conditions, and the performance has been compared with the proposed ones. The simulated results prove the excellence of proposed designs in different performance parameters like leakage power, energy-delay-product (EDP), PDP, layout area compared with the recent designs. The PDPdq value has a reduction of 95.9per cent (TCRSR), 96.6per cent (S-TCRSR) and 97per cent (FST in TCRSR) with that of a conventional shift register (TGSR). Originality/value The performance of proposed low-power SR designs is enhanced using EHO algorithm. The optimized performance results have been compared with a few optimization algorithms. It is for the first time that EHO algorithm is implemented in memory elements.

show abstract

Section: Resultsmentioning

confidence: 99%

Power and area-efficient register designs involving EHO algorithm

Sabu

Batri

2020

View full text Add to dashboard Cite

show abstract

“…Redundant formation of hardened designs often causes high overheads. Pulse-Triggered Flip-Flop (PFF) is an option to help in penalty reducing or area diminishing due to its simple and compact structure [17,18]. However, high power consumption due to redundant switching activities and contention mechanism is usually an issue [14,19,20,21].…”

Section: Introductionmentioning

confidence: 99%

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

Jin

Zhang

et al. 2021

IEICE Electron. Express

View full text Add to dashboard Cite

A power-efficient Single Event Upset (SEU) -tolerant pulsetriggered flip-flop design is presented. The dual-modular redundant design takes advantage of concise formation of pulse-triggered designs, and avoids the disadvantages of it, such as high power consumption. Clock-gating scheme is applied to reduce power consumption. The static configuration and the avoidance of contention mechanism led to the balance of power consumption, speed and SEU tolerance. The SEU tolerance is evaluated by means of SEU cross section, which is significantly lower than conventional D flip-flop. The proposed flip-flop is designed in 55nm CMOS technology to evaluate performances. The proposed design achieves the lowest power consumption, which is even lower than conventional D flip-flop. Although the speed is sacrificed, the lowest power-delay product is achieved among hardened designs. The proposed design provides solution to speedinsensitive and power-constrained applications.

show abstract

“…According to Moore's law, it is anticipated that the number of transistors on a chip doubles every 2 years [1]. However, traditional CMOS technology is facing a variety of challenges, in which limitations of the CMOS technology require looking for other technologies to overcome these limitations [2].…”

Section: Introductionmentioning

confidence: 99%

A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit

et al. 2019

View full text Add to dashboard Cite

Memristor-based digital logic circuits open new pathways for exploring advanced computing architectures, which provide a promising alternative to conventional IC technology. In several memristor-based logic design methods, the memristor ratioed logic (MRL) is compatible with traditional CMOS technology. Two kinds of carry-lookahead adders (CLA) based on the hybrid CMOS-memristor structure are proposed, within which one is based on MRL logic, and the other is an improved one that is implemented by MRL universal gate (MRLUG). The proposed CLAs are verified by theoretical analyses and simulations, showing that the proposed design method requires fewer memristors and CMOSs than the IMP-based or CMOS-based CLAs, which means smaller circuit size and lower power consumption.INDEX TERMS Memristor, logic circuit, CLA.

show abstract

A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power

Cited by 24 publications

References 31 publications

Power and area-efficient register designs involving EHO algorithm

Power and area-efficient register designs involving EHO algorithm

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit

Contact Info

Product

Resources

About