A novel data acquisition scheme based on a low-noise front-end ASIC and a high-speed ADC for CZT-based PET imaging

Abstract

In this paper, we present a novel data acquisition scheme based on a low-noise front-end readout ASIC and a high speed ADC for PET imaging systems based on cadmium zinc telluride (CZT) detectors. A charge-sensitive amplifier(CSA), a pulse shaper and a driving buffer are integrated for each CZT detector pixel. The specifications of the ASIC are dependent on the dimension of the CZT detector. Eight shaping voltages are sampled and digitized. The data from the ADC is collected by a programmable FPGA which can run an algorithm to calculate the peak value of the shaped voltages and the trigging timing of the shaped pulses. To achieve good noise performances and to realize a flexible front-end electronic system, the front-end ASIC and the ADC are not integrated together. Two ASICs as well as the FPGA chip will be bonded directly on the board. Both the front-end readout chip and the ADC chip are designed in 0.35 μm CMOS processing. The input range of the front-end ASIC is from 2000 e-to 40000 e-. The equivalent noise charge (ENC) is below 200 e-. The shaping time is about 1.5 μs. The simulated results show that the proposed method can achieve good spatial resolution and good detection efficiency, and meanwhile, the time resolution of the PET system is greatly improved.

Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager

“…Based on the proposed layout of the MIM capacitor unit, as shown in figure 8, an optimum uniform routing method is proposed in figure 9(a). Figure 9 A, B, C, D, E, F, G) which correspond to the capacitors (C, 2C 2 2 C, 2 3 C, 2 4 C, 2 5 C, 2 6 C,) in figure 7. The capacitor marked as * is the dummy capacitor which is used to make the edge capacitors of the capacitor array keep the same environment with other internal capacitors.…”

“…The output voltage of the shaper is sampled by a high-speed ADC. In our solution, at least eight voltage values of the shaped pulse are sampled and digitized [5][6][7]. The data from the ADC is collected by a programmable FPGA which can run an algorithm to calculate the peak value of the shaped pulse.…”

Evaluation of a Wobbling Method Applied to Correcting Defective Pixels of CZT Detectors in SPECT Imaging

“…The CZT detector consists of a semiconducting crystal that is bump-bonded to a large area ASIC and packaged with a high performance data acquisition system. Recently, great progress has been made in electronics [ 9 , 10 , 11 , 12 ] and crystal growing [ 13 , 14 ]. However, there are still some defective pixels, showing degraded features, such as split or broadening spectral peaks and extraordinarily low or high response, especially for pixels with smaller sizes or at the edge of module.…”

Ανάπτυξη συστήματος συλλογής δεδομένων βασισμένο σε προγραμματιζόμενα ηλεκτρονικά (FPGAs) για εφαρμογή σε συστήματα μοριακής απεικόνισης

“…Στην κατεύθυνση της κατασκευής μικρών και ευέλικτων συστημάτων απόκτησης δεδομένων αρκετές ομάδες αντικατέστησαν μέρος των αναλογικών ηλεκτρονικών με ψηφιακά ολοκληρωμένα κυκλώματα ειδικού σκοπού (Application Specific Integrated Circuit -ASIC). Συνήθως το συνολικό σύστημα περιλαμβάνει και ένα FPGA για τον έλεγχο των αναλογικών μερών αλλά και για επεξεργασία των σημάτων [70,71,72,73]. Ενώ τα συ-Κεφάλαιο 3.…”