A novel CVD-SiBCN Low-K spacer technology for high-speed applications

Ko, Chih-Hsin; Kuan, Ta-Ming; Zhang, Kangzhan; Tsai, Gene; Seutter, S.M.; Wu, Chien-Hung; Wang, T.J.; Ye, C.N.; Chen, H.W.; Ge, Chung-Hu; Wu, Kenneth; Lee, Wan-Hsin

doi:10.1109/vlsit.2008.4588581

Cited by 20 publications

(9 citation statements)

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“…Raised source and drain regions and silicidation as well as low Schottky barrier source and drain contacts have been proposed those last years to minimize their impact on the static and dynamic transistor behaviors. Modification of the device architecture such as introduction of faceted source and drain , low‐k spacer materials , gate capping layer thickness, and gate height have been used recently to reduce the fringing parasitic capacitance effect. Concerning the substrate coupling effects, FinFET with narrow fins is intrinsically immune, and they can be avoided in the case of UTBB with the introduction of the ground plane contact.…”

Section: Discussionmentioning

confidence: 99%

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Raskin

2013

Int J Numerical Modelling

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SUMMARYSeveral physical phenomena specific to silicon-on-insulator metal-oxide-semiconductor field-effect transistors, such as floating body effects, self-heating, and substrate coupling, are described and modeled. Small-signal equivalent circuit of ultra-thin body and thin buried oxide and fin field effect transistor (FinFET) are extracted, and their radio frequency figures of merit as well as their advantages and limitations are presented. We demonstrate the importance of performing wideband characterization at the early stage of the technology development in order to identify the device weaknesses and come up with technological solutions to overcome those. With the ongoing downscaling of the metal-oxide-semiconductor devices, the surrounding of the transistor, that is, the contacts, the access lines, and the substrate, starts to play a major role on the transistor behavior. There is an urgent need to develop adequate models for the new generation of devices valid over a wide frequency band.

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Section: Discussionmentioning

confidence: 99%

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Raskin

2013

Int J Numerical Modelling

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“…(5) the limit K o k → K SP , and hence Equ. (6), that the separation between the electrodes is very small in comparison to the length of the electrodes [10]. This is certainly not the case in short channel high-k dielectric SOI-MOSFETs.…”

Section: Thin Film Transistor Tft Modelmentioning

confidence: 99%

“…By increasing in the surface potential and decreasing the threshold voltage. It has been demonstrated a suitable low-permittivity low-K gate sidewall spacer dielectric novel nanocomposite PTFE/SiO2, Ksp=2.9, which can replace Si3N4, Ksp=7.5 [4][5][6][7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Effect of Novel Nanocomposite Materials for Enhancing Performance of Thin Film Transistor TFT Model

Mobarak

Atef

2016

IJAAS

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The potential impact of high permittivity gate dielectrics on thin film transistors short channel and circuit performance has been studied using <a name="OLE_LINK110"></a><a name="OLE_LINK118"></a>highly accurate analytical models. In addition, the gate-to-channel capacitance and parasitic fringe capacitances have been extracted. The suggested model in this paper has been <a name="OLE_LINK37"></a><a name="OLE_LINK36"></a>increased the surface potential and decreased the <a name="OLE_LINK93"></a><a name="OLE_LINK92"></a>threshold voltage, whenever the conventional silicon dioxide gate dielectric<a name="OLE_LINK290"></a><a name="OLE_LINK280"></a> is replaced by high-K gate dielectric novel nanocomposite PVP/La2O3Kox=25. Also, it has been investigated that a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance, whenever the conventional silicon nitride is replaced by low-K gate sidewall spacer dielectric novel nanocomposite PTFE/SiO2Ksp=2.9. Finally, it has been demonstrated that using low-K gate sidewalls with high-K gate insulators can be decreased the gate fringing field and threshold voltage. In addition, fabrication of nanocomposites from polymers and nano-oxide particles found to have potential candidates for using it in a wide range of applications in low cost due to low process temperature of these nanocomposites materials.

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“…Modern CMOS technologies make extensive use of spacer layers with different dielectric thicknesses [25]. An example is considered here, where the first spacer has a dielectric constant 1 = 3.9 · 0 lower than the outer spacer ( 2 = 7 · 0 ), as shown in Fig.…”

Section: A Different Dielectric Constantsmentioning

confidence: 99%

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

Hiblot

Rafhay

Bœuf

et al. 2015

IEEE Trans. Electron Devices

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In this paper, the main MOSFET parasitic capacitances of planar devices (i.e., bulk, Fully depleted silicon-on-insulator (FDSOI), and planar double gate) are computed using two successive conformal mapping transforms. First, the structure is mapped to the real axis of the complex plane, and then the second transform, deduced directly from the Schwarz-Christoffel theorem, reduces the capacitance to the trivial parallel electrodes case. This second step involves elliptic integrals, which provide a generic expression for all parasitic capacitances. This method is later compared against other models based on conformal mapping. Finally, the results are validated with finite-element method simulations of the inner and outer fringe capacitances in different architectures, including metallic contacts and raised and faceted junctions.Index Terms-CMOS, compact model, conformal mapping, electrostatic, elliptic integrals, Model for Assessment of CMOS Technologies and Roadmaps (MASTAR), MOSFET, parasitic capacitance, roadmap.

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A novel CVD-SiBCN Low-K spacer technology for high-speed applications

Cited by 20 publications

References 2 publications

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Effect of Novel Nanocomposite Materials for Enhancing Performance of Thin Film Transistor TFT Model

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

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