A Novel Co-Design Approach for Soft Errors Mitigation in Embedded Systems

Cuenca-Asensi, Sergio; Martínez-Álvarez, Antonio; Restrepo-Calle, Felipe; Palomo, F.R.; Guzmán-Miranda, H.; Aguirre, M.A.

doi:10.1109/tns.2011.2112379

Cited by 33 publications

(17 citation statements)

References 30 publications

(17 reference statements)

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“…The results presented in this paper focus only on the evaluation of the proposed approach to harden the configuration data of microcontroller peripherals and interrupts. The SEU and SET sensitivities of the microprocessor core using partial hardware and software hardening have been analyzed previously in [16] and [17], respectively.…”

Section: Resultsmentioning

confidence: 99%

A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications

Martínez-Álvarez

Restrepo-Calle

Cuenca-Asensi

et al. 2016

IEEE Trans. Dependable and Secure Comput.

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Abstract-Integrity assurance of configuration data has a significant impact on microcontroller-based systems reliability. This is especially true when running applications driven by events which behavior is tightly coupled to this kind of data. This work proposes a new hybrid technique that combines hardware and software resources for detecting and recovering soft-errors in system configuration data. Our approach is based on the utilization of a common built-in microcontroller resource (timer) that works jointly with a software-based technique, which is responsible to periodically refresh the configuration data. The experiments demonstrate that non-destructive single event effects can be effectively mitigated with reduced overheads. Results show an important increase in fault coverage for SEUs and SETs, about one order of magnitude.

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Section: Resultsmentioning

confidence: 99%

A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications

Martínez-Álvarez

Restrepo-Calle

Cuenca-Asensi

et al. 2016

IEEE Trans. Dependable and Secure Comput.

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“…This approach presents the limitation that it cannot be applied with on-chip cache memories. Finally, different hybrid approaches, based on selective hardening, are evaluated in terms of execution time and memory overheads and fault detection capability in [18] and [19]. But the presented hybrid solutions are intrusive, meaning that the microprocessor used must be redesigned.…”

Section: Background and Related Workmentioning

confidence: 99%

“…The software-based approaches are very flexible and can be used with Commercial Off-TheShelf (COTS) microprocessors, because no internal modifications to the microprocessor are required. However, they may produce large overheads in processing time and storage needs [18], [19]. These can be particularly very large for control-flow checking, because a large amount of signatures need to be stored and checked very often.…”

Section: Introductionmentioning

confidence: 99%

Efficient Mitigation of Data and Control Flow Errors in Microprocessors

Parra

Lindoso

Portela

et al. 2014

IEEE Trans. Nucl. Sci.

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Abstract-The use of microprocessor-based systems is gaining importance in application domains where safety is a must. For this reason, there is a growing concern about the mitigation of SEU and SET effects. This paper presents a new hybrid technique aimed to protect both the data and the control-flow of embedded applications running on microprocessors. On one hand, the approach is based on software redundancy techniques for correcting errors produced in the data. On the other hand, control-flow errors can be detected by reusing the on-chip debug interface, existing in most modern microprocessors. Experimental results show an important increase in the system reliability even superior to two orders of magnitude, in terms of mitigation of both SEUs and SETs. Furthermore, the overheads incurred by our technique can be perfectly assumable in low-cost systems.

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“…It consists of protecting only the most critical parts of the designs. This partial protection can be achieved by means of selective redundancy applied to: hardware [6][7], software [8][9], or by means of hybrid hardware/software approaches [10][11].…”

Section: Introductionmentioning

confidence: 99%

“…In particular for processor-based systems, a well-known strategy consists of protecting only the most critical registers in the microprocessor register file [8][9][10][11].Thus, it is evident the necessity to identify the most critical registers properly during an early design stage in order to facilitate the selection of the hardened set of registers. A proper selection of registers determines to achieve good efficiency/cost tradeoffs for the designed solution and, at the same time, permits to explore the design space effectively, avoiding costly explorations guided by brute force strategies [24].…”

Section: Introductionmentioning

confidence: 99%

Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors

et al. 2015

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Abstract-There is an increasing concern to reduce the cost and overheads during the development of reliable systems. Selective protection of most critical parts of the systems represents a viable solution to obtain a high level of reliability at a fraction of the cost. In particular to design a selective fault mitigation strategy for processor-based systems, it is mandatory to identify and prioritize the most vulnerable registers in the register file as best candidates to be protected (hardened).This paper presents an application-based metric to estimate the criticality of each register from the microprocessor register file in microprocessor-based systems. The proposed metric relies on the combination of three different criteria based on common features of executed applications. The applicability and accuracy of our proposal have been evaluated in a set of applications running in different microprocessors. Results show a significant improvement in accuracy comparing to previous approaches and regardless the underlying architecture.

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A Novel Co-Design Approach for Soft Errors Mitigation in Embedded Systems

Abstract: Abstract-A novel proposal to design radiation-tolerant embedded systems combining hardware and software mitigation techniques is presented. Two suites of tools are developed to automatically apply the techniques and to facilitate the tradeoffs analyses.

Cited by 33 publications

References 30 publications

A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications

A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications

Efficient Mitigation of Data and Control Flow Errors in Microprocessors

Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors

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