A novel cache architecture with enhanced performance and security

Abstract

Abstract-Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent findings on efficient attacks based on information leakage in caches have also brought the security issue up front. Design for security introduces even more restrictions and typically leads to significant performance degradation. This paper presents a novel cache architecture that can simultaneously achieve the above goals. Specifically, cache miss rates are reduced with dynamic remapping and longer cache indices, access-time overhead overcome with astute low-level circuit design, and information leakage thwarted by a security-aware cache replacement algorithm together with the performance enhancing mechanisms. We present both theoretical analysis and experimental results, using the SPEC2000 suite to evaluate the cache miss behavior, and CACTI and HSPICE to validate the circuit design. Our results show that the proposed cache architecture has low miss rates comparable to a highly associative cache and short access times and power efficiency close to that of a direct-mapped cache. At the same time it can thwart cache-based software side-channel attacks, providing both legacy and security-enhanced software a much higher degree of security. Additional benefits that the proposed cache architecture can bring, like fault tolerance and hot-spot mitigation, are also discussed briefly.

Ghost loads

“…For attacks involving a different execution context, we need to make sure that the entries in the GhB belonging to different contexts are isolated. Previous works [10,11,15,18,20,21,26,27,30,36,37] have already identified solutions to achieve this in regular caches, but given the special characteristics of the GhB, we propose the following:…”

“…This is not an attractive solution for general-purpose computing, as speculative execution offers substantial performance benefits. (2) Speculate but obfuscate microarchitectural changes so that an attacker cannot discern microarchitectural changes due to speculation [35][36][37]. (3) Speculate but do not change microarchitectural state until the speculation can be resolved.…”

CacheSCDefender: VMM-based Comprehensive Framework against Cache-based Side-channel Attacks

“…Such a method is good to protect specific application, but would not be widely applied since each target application needs to be modified. Another type of random permutation is randomizing the mapping from machine address to cache sets [9,10,22], thus making information inferred from cache operations cannot reveal the memory access pattern of the victim. However, all current works of this type requires new design of hardware, leading to bad compatibility with current cloud platforms.…”

“…Accordingly, there are a large number of solutions proposed for defending against cache-based side-channel attacks. Most of them can be divided into two types: one requires modifying the hardware [9] [10], which imposes bad compatibility with current platform; the other needs to alter systems [11] [12] or vulnerable applications [13,14,15], which is too specific and cannot be applied widely. There are also some defense methods proposed for VMM layer [16,17,18,19,20], which might influence the operation of normal applications [16], or would only defend against a portion of cache attacks [17], or greatly reduce benefits of cache sharing [18] [19], or would bring too much overhead [20].…”

A Survey of Timing Channels and Countermeasures

“…Another cache architecture is proposed in [Wang and Lee 2008] to reduce cache miss rate, to overcome access-time overhead and to thwart information leakage. They have used a security-aware cache replacement algorithm to thwart information leakage.…”