A Novel BIST TPG for Testing of VLSI Circuits

Gunavathi,; Paramasivam,; Lavanya,; Umamageswaran,

doi:10.1109/iciinfs.2006.347131

Cited by 3 publications

(4 citation statements)

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“…In this paper low power architecture [9] for test pattern generator is been presented. The architecture consumes less power, and can be effectively used for the testing [10] of digital integrated chips.…”

Section: Literature Reviewmentioning

confidence: 99%

Implementation of Low Power Test Pattern Generator for Digital Integrated Circuits

Vardhana¹,

Rajan²

2016

IJHIT

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Section: Literature Reviewmentioning

confidence: 99%

Implementation of Low Power Test Pattern Generator for Digital Integrated Circuits

Vardhana¹,

Rajan²

2016

IJHIT

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“…With the development of fabrication technologies, the fault occurrence probability increases in the memories used for memory intensive applications [1]. The fault diagnosis methods give the way to detect the faulty sites and the redundancy analysis (RA) algorithms provide the repair solutions for these faulty sites [2–5]. The repair solutions are in the form of availing the spare rows and columns to the faulty locations such that the memory is being operational [6, 7].…”

Section: Introductionmentioning

confidence: 99%

Novel modified memory built in self‐repair (MMBISR) for SRAM using hybrid redundancy‐analysis technique

Pundir

2019

IET Circuits, Devices & Systems

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The article presents a new augmented and improved MMBISR for SRAM using hybrid redundancy analysis (HRA). The presented algorithm is the augmented version of essential spare pivoting (ESP) and local repair most (LRM). The algorithm proposes the best solution by providing optimised set of row and column combination which were suitable for the repairing process. In the proposed redundancy analysis (RA) algorithm, the fault dictionary can be updated or fixed concurrently, according to MBIST needs and supplied control signals. The row and column pivots and repair requests are also serviced according to precedency list prepared by the comparing actions. The comparative analysis with LRM and ESP-RA algorithms shows that the proposed algorithm has reduced complexity and tracing time in terms of implementation and in terms of finding row and column pivots. For the implementation, a MBISR hardware structure is designed and tested using suitable VHDL descriptions that were targeted for Virtex-5, xc5vlx30 FPGA. The results were also justified that the proposed algorithm is quite effective as the repair rate is increased up to 4% compared to the ESP. However, some nominal area penalty is observed as compared to ESP.

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“…A dual-speed LFSR scheme [20] is based on two different speed LFSRs to decrease the circuit's overall internal activity. Its objective is to decrease the circuit's overall internal activity by connecting inputs that have elevated transition densities to the slow-speed LFSR.…”

Section: By Reducing the Transitionsmentioning

confidence: 99%

“…The proposed technique represses transitions of patterns using the k-value which is a standard that is obtained from the distribution of TMW to observe over transitive patterns causing high-power dissipation in a scan chain. In [26], a TPG based on Read-Only Memory (ROM) is carefully designed to store the test vectors with minimum area over the conventional ROM. This reduces the number of CMOS transistors significantly when compared to that of LFSR/Counter TPG.…”

Section: By Reducing the Transitionsmentioning

confidence: 99%

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

2011

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Test power is the major issue for current generation VLSI testing. It has become the biggest concern for today's SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques. To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed for their suitability to IP core-based SoC.

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A Novel BIST TPG for Testing of VLSI Circuits

Cited by 3 publications

References 0 publications

Implementation of Low Power Test Pattern Generator for Digital Integrated Circuits

Implementation of Low Power Test Pattern Generator for Digital Integrated Circuits

Novel modified memory built in self‐repair (MMBISR) for SRAM using hybrid redundancy‐analysis technique

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

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