A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application

Thakur, Garima; Sohal, Harsh; Jain, Shruti

doi:10.1007/s00034-021-01741-6

Cited by 15 publications

(3 citation statements)

References 27 publications

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“…The recommended MCSC-FA was able to produce superior ADP performance in terms of LUT-FF, LUTs, Power (W), Delay (nS), and Slice registers. Comparing the suggested 32-bit Hybrid-performance PPA's to that of common 32-bit adders like LOCA [17], BCSA [18], and BSA [20] is shown in Table 2. The suggested 32-bit Hybrid-PPA outperformed the competition in terms of LUT-FF, LUTs, Power (W), Delay (nS), and Slice registers.…”

Section: Resultsmentioning

confidence: 99%

“…Intel's powerful central processing unit (CPU) can now accommodate about two billion transistors thanks to the introduction of manufacturing nanotechnology and the reduction in device size. The authors in [20] carried out the approximation adders that were based on QCA. In addition, the multipliers themselves are made with the help of approximation adders.…”

Section: Literature Surveymentioning

confidence: 99%

“…Short circuit power is the name given to the power that is lost if both NMOS and PMOS transistors are switched on simultaneously. Another factor that contributes to this kind of power is the rise and fall timings of the input signals that the gate receives [5]. One way for lowering the amount of power that is lost due to a short circuit is making adjustments to the rise and fall periods of the input waveform.…”

Section: Introductionmentioning

confidence: 99%

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Implementation of low power N-bit hybrid parallel prefix adder using Xilinx-ISE

Gopathoti¹,

Sruthi²

2023

IJSMEM

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Recently, digital circuitry has demanded a decrease in space and power by decreasing time while simultaneously improving performance in speed. This has resulted in a need for more efficient use of the available space. Adders are fundamental components that are used in the construction of digital circuits. As a consequence of this, the performance of adders has to be improved in order to enhance the performance of integrated circuits that are used in the real world. The creation of a novel parallel prefix adder (PPA) architecture known as Hybrid PPA is the primary topic of this article. Hybrid PPA makes use of full carrier generation (FCG), full sum generation (FSG), half carry generation (HCG), and half sum generation (HSG) blocks. In addition to this, the N-bit Hybrid-PPA is constructed with features that may be reconfigured, and these features utilise square root additions through modified sum carry selection (MSCS). In addition, the implementation of multiplexer switching logic, which selects the whole sum bits and carry bits in a high-speed manner, reduces the amount of propagation time necessary for the generation of the sum and carry output. The results of the simulation show that using the proposed Hybrid PPA results in a reduction in area, latency, and power consumption when compared to using basic adders or approaches that are considered to be state of the art.

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Section: Resultsmentioning

confidence: 99%

Section: Literature Surveymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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