Implementation of low power N-bit hybrid parallel prefix adder using Xilinx-ISE

Abstract

Recently, digital circuitry has demanded a decrease in space and power by decreasing time while simultaneously improving performance in speed. This has resulted in a need for more efficient use of the available space. Adders are fundamental components that are used in the construction of digital circuits. As a consequence of this, the performance of adders has to be improved in order to enhance the performance of integrated circuits that are used in the real world. The creation of a novel parallel prefix adder (PPA) architecture known as Hybrid PPA is the primary topic of this article. Hybrid PPA makes use of full carrier generation (FCG), full sum generation (FSG), half carry generation (HCG), and half sum generation (HSG) blocks. In addition to this, the N-bit Hybrid-PPA is constructed with features that may be reconfigured, and these features utilise square root additions through modified sum carry selection (MSCS). In addition, the implementation of multiplexer switching logic, which selects the whole sum bits and carry bits in a high-speed manner, reduces the amount of propagation time necessary for the generation of the sum and carry output. The results of the simulation show that using the proposed Hybrid PPA results in a reduction in area, latency, and power consumption when compared to using basic adders or approaches that are considered to be state of the art.