A novel array architecture and routing structure for massive-MIMO detection in Coarse-Grained Reconfigurable Architecture platform

Abstract

Based on the data flow feature analysis of the MIMO detection algorithms, a more efficient array architecture and a multi-hierarchical routing structure are proposed in the Coarse-Grained Reconfigurable Architecture platform, named Reconfigurable Signal Processor 2.0 (RaSP2.0) in this paper. The proposed design with higher throughput requires less hardware resource and has more efficient routing structure when compared with the first generation of RaSP. Implemented in TSMC 40nm technology, the single core of RaSP2.0 occupies 1.02 mm 2 and is capable of running at 500MHz. The experimental results show that the area of RaSP2.0 reduces 63% compared with RaSP when normalized to 96-order matrix inversion operation. The hardware efficiency of QR decomposition (QRD) operation in the case of 4×4 matrix is improved by 1~3.17 times than the other architectures. In addition, the RaSP2.0 can realize the 96-order matrix inversion operation via only one single mapping, which can provide higher throughput.

Low-Latency Parallel Hermitian Positive-Definite Matrix Inversion for Massive MIMO

“…end Using the scheduling algorithm in Algorithm 1, the latency of the three different algorithms is found. First of all, by utilizing an unlimited number of PEs, each with a latency of one clock cycle, the theoretically lowest latency is obtained 5 . This corresponds to scheduling all possible operations in every clock cycle and the results of the operations are available in the next clock cycle.…”

“…Since the latency of all operations is the same, this is also a least slack time approach 5. In this case, the scheduling algorithm is guaranteed to be optimal.…”