2021 IEEE Workshop on Signal Processing Systems (SiPS) 2021
DOI: 10.1109/sips52927.2021.00013
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Low-Latency Parallel Hermitian Positive-Definite Matrix Inversion for Massive MIMO

Abstract: In this work, the effect of latency for three different positive definite matrix inversion algorithms when implemented on parallel and pipelined processing elements is considered. The work is motivated by the fact that in a massive MIMO system, matrix inversion needs to be performed between estimating the channels and producing the transmitted downlink signal, which means that the latency of the matrix inversion has a significant impact on the system performance. It is shown that, despite the algorithms having… Show more

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