A Novel Approach to Reduce Packet Latency Increase Caused by Power Gating in Network-on-Chip

Wang, Peng; Niknam, Sobhan; Wang, Zhiying; Stefanov, Todor

doi:10.1145/3130218.3130220

Cited by 11 publications

(2 citation statements)

References 15 publications

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“…163 router without cause gating, this airway, with only learning in connected approaches. The constituent is midget return and the formulation can forestall on normal 52.19% of their complete cause intake in the NoC, these is equal with the 59.39% and 57.05% knowledge saved in elate methods [18].…”

Section: Low Power Network On Chip Architectures: a Survey (Muhammad Raza Naqvi)mentioning

confidence: 99%

Low power network on chip architectures: A survey

Naqvi

2020

Comput. Sci. Inf. Technol.

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Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

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Section: Low Power Network On Chip Architectures: a Survey (Muhammad Raza Naqvi)mentioning

confidence: 99%

Low power network on chip architectures: A survey

Naqvi

2020

Comput. Sci. Inf. Technol.

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“…Wang et al [18] initiate a new system of tariff framework DB and learning on to change a person group for businesslike DB-based noesis gating to be trim this weakness. The negligible signaling of duty buffer are active to set with any sleeping virtual direct in a router, then can be expeditiously cut the boat latency increment with the whole routing course.…”

Section: Pipeline Stage Reductionmentioning

confidence: 99%

Low power network on chip architectures: A survey

Muhammad Raza Naqvi

2021

Comput Sci Inf Technol

View full text Add to dashboard Cite

Mostly communication now days is done through system on chip (SoC) models so, network on chip (NoC) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

show abstract