A Novel Approach for Reversible Realization of 3:8 Decoder Circuit with Optimized Performance Parameters

Optimized Design of Decoder 2 to 4, 3 to 8 and n to 2n using Reversible Gates

“…-Number of constant inputs: 50 % compared to design2 [13], design [11] and design [18], 33.33 % compared to design3 [9], design [14], design [12] and design [16].…”

“…-Quantum cost: 27.27 % compared to design3 [9], design [10], design [11], design [16], 46.66 % compared to design [14].…”

“…6) RI Gate : A reversible gate 3 * 3 having for inputs A, B and C as outputs P = B, Q = AB'+BC C and R = AB C the quantum cost of the RI gate is equal to QC = 4, its Hardware complexity is worth HC = 1 α+3β+1δ [8] 9) TR Gate : A reversible gate 3 * 3 having for inputs A, B and C as outputs P = A, Q = A B, R = AB' C, S = AB C bigoplus D the quantum cost of the TR gate is equal to QC = 4 and its Hardware complexity is equal to HC = 2 α + 1 β+1 δ [20] 10)DVSM Gate : A reversible gate 4 * 4 having for inputs A, B, C and D as outputs P = AB A'C, Q = AB' A'C, R = A'B AC'and S= D AC A'B' the quantum cost of the TR gate is equal to QC = 11 and its Hardware complexity is equal to HC = 5 α + 7 β+3 δ [11] 11)MFRG1 Gate : A reversible gate 3 * 3 having for inputs A, B and C as outputs P = A, Q = A'B AC', R = A'C AB, the quantum cost of the TR gate is equal to QC = 4 and its Hardware complexity is equal to HC = 2 α + 4 β+2 δ [12] 12)MFRG2 Gate : A reversible gate 3 * 3 having for inputs A, B and C as outputs P = A', Q = A'B AC, R = A'C AB, the quantum cost of the TR gate is equal to QC = 4 and its Hardware complexity is equal to HC = 2 α + 4 β+1 δ [12] 13) OM Gate : A reversible gate 3 * 3 having for inputs A, Band C as outputs P = A, Q = AB C', R = A'B C',the quantum cost of the OM gate is not mentioned in the literature and its hardware complexity is HC = 2 α + 2 β+2 δ [13] 14) SOM Gate : A reversible gate 4 *4 having for inputs A, B, C and D as outputs P = AB C D, Q = AB' C, R = A'B C D S=A'B' C D,the quantum cost of the SOM gate is not mentioned in the literature and its hardware complexity is HC = 5 α + 4 β+2 δ [13] 15) UM Gate : A reversible gate 6 *6 having for inputs A, B, C ,D,E and F as outputs P = A, Q = AB C', R = A'B C' S=A D, T=DE F' and U=D'E F' the quantum cost of the SOM gate is not mentioned in the literature and its hardware complexity is HC = 5 α + 4 β+4 δ [13] 16)RD Gate : A reversible gate 4 *4 having for inputs A, B, C and D as outputs P = AB D, Q = (A+B)' D, R = (A+B') C D S=AB' D, the quantum cost of the RD gate is 8 and its hardware complexity is HC = 5 α + 2 β+2 δ…”

“…6. by using 1 reversible gate of the NKHD by assigning to the third input the value 1 and to the fourth, fifth and sixth input the value 0 and concerning its performance criteria we have CG = 1, NGO = 2, NCI = 4, QC = 11 and HC = 6α + 4 β+1 δ 5) Design7: In 2018 Vandana Shukla [11]proposed 1 design of decoder 2 to 4 as shown in Fig. 7.…”

“…6. 5) Design7: In 2018 Vandana Shukla [11] proposed a design of the decoder 3 to 8 using an DVSM reversible gate by assigning to the third and the fourth input the value 1 and for 4 FRG reversible gates assigning to the third input for each the value 0 concerning its performance criteria we have CG = 5, NGO = 1, NCI = 6, QC = 31 and HC=13 α + 23β+7 δ as shown in Fig. 19.…”