A novel &amp;amp;#x201C;divide and conquer&amp;amp;#x201D; testing technique for memristor based lookup table

Hongal, Veeresh Anilkumar; Kotikalapudi, Raghavendra; Kim, Yong-Bin; Choi, Minsu

doi:10.1109/mwscas.2011.6026406

Cited by 10 publications

(1 citation statement)

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“…Therefore, testing multiple transistors at the same time was needed. This was done by using divide-and-conquer testing technique proposed in [9]. However, this technique does not consider sneak-paths (unwanted current flow) in crossbar memories.…”

Section: Introductionmentioning

confidence: 99%

On the Production Testing of Memristor Ratioed Logic (MRL) Gates

Emara¹,

Madian²,

Amer³

et al. 2016

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This paper focuses on the production testing of Memristor Ratioed Logic (MRL) gates. MRL is a family that uses memristors along with CMOS inverters to design logic gates. Two-input NAND and NOR gates are investigated using the stuck at fault model for the memristors and the five-fault model for the transistors. Test escapes may take place while testing faults in the memristors. Therefore, two solutions are proposed to obtain full coverage for the MRL NAND and NOR gates. The first is to apply scaled input voltages and the second is to change the switching threshold of the CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration. It is proven that three ordered test vectors are needed for full coverage in MRL NAND and NOR gates, which is different from the order required to obtain 100% coverage in the conventional NAND and NOR CMOS designs.

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Section: Introductionmentioning

confidence: 99%