A novel AES-256 implementation on FPGA using co-processor based architecture

Sau, Suman; Paul, Rourab; Biswas, Tanmay; Chakrabarti, Amlan

doi:10.1145/2345396.2345499

Cited by 5 publications

(4 citation statements)

References 9 publications

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“…[7] supports 128,196,256 bit key with normal performance. In design [3], it achieves low-cost, but it doesn't support all 5 kinds of mode and have lower throughput than our design. Design proposed in [4] achieves higher throughput with respect to our design, but it takes much more resources than our design.…”

Section: Vmentioning

confidence: 82%

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An Implementation of Configurable and Small- Area AES IP Core Oriented Avalon Bus

Tao¹,

Zhang²,

Song³

2015

Advances in Intelligent Systems Research

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The Advanced Encryption Standard (AES) issued by the National Institute of Standards and Technology in 2001 has become the new widely-used symmetric block cipher standard. A lot of efforts have been made on the various hardware implementations of the AES algorithm. Some focus on achieving low-cost constructions, while others focus on designing high throughput. Given the specific requirement of wireless communication and portable devices, this article presents an AES IP core with an acceptable trade-off between performance and area. By introducing composite fields Sboxes and researching optimization of MixColumn can reduce resources. The AES IP is designed based on Avalon bus. It is compatible with five modes including ECB, CBC, OFB, CFB, and CTR. 128,196,256 bits key are also supported. Meanwhile, it can be flexibly configured according to the specific circumstances. This design and implementation of the AES core has a certain value for the generalization the wireless communication terminal hardware platform.

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Section: Vmentioning

confidence: 82%

“…Research efforts have been made for the implementation of AES security algorithms on hardware for embedded system applications using FPGA. In the designs [2] [3], the core is designed with Microblaze processor core. [4] [5] use Altera NIOS II core.…”

Section: Introductionmentioning

confidence: 99%

An Implementation of Configurable and Small- Area AES IP Core Oriented Avalon Bus

Tao¹,

Zhang²,

Song³

2015

Advances in Intelligent Systems Research

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“…The frequency division principle is a fundamental operational idea that facilitates the reduction of a high frequency signal to a lower frequency. The aforementioned approach entails the reduction of signal frequency by the process of dividing the periodic waveform of the input signal into equidistant segments, afterwards outputting a fraction of said waveform [4].…”

Section: Frequency Dividermentioning

confidence: 99%

Verilog-based digital clock design methodology

Wang

2023

TNS

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A digital electronic clock is a sophisticated instrument that employs digital circuits to render the timehours, minutes, and secondsin a digital format. This paper delves into the intricate design journey of creating a basic digital clock using the powerful Verilog HDL paired with a seven-segment digital tube. The core objective revolves around the realization of the clocks essential features, emphasizing both timing mechanics and its visual display. The architecture of the digital clock circuit is a seamless integration of three pivotal modules: the frequency divider, which ensures accurate time intervals; the counter, which keeps track of elapsed time; and the decoder, responsible for converting raw data into a format suitable for display. The clocks tangible representation of time is vividly brought to life on a light-emitting diode (LED) display of the seven-segment digital tube. This setup magnificently showcases two-digit representations for hours, minutes, and seconds, streamlining the users experience. Rigorous simulation revealed that the system adeptly meets its operational mandate, functioning seamlessly as a digital clock and thereby aligning perfectly with the stipulated design criteria.

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“…Probability. Therefore, in the environment, people need to actively cultivate talents in this area, and digital clocks also need people to actively improve, discover, and create new and better design methods [10].…”

Section: Facing Challengementioning

confidence: 99%

A Review of Design of Digital Clock Based on Verilog HDL

Li¹,

Li²,

Zeng³

et al. 2023

HSET

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With the development of electronic technology, digital clocks have added many functions that facilitate people's lives, Digital electronic clock is a device that uses digital circuits to realize the digital display of time, minutes, and seconds. This paper mainly discusses how to use Verilog HDL to design a simple digital clock and realize the basic functions such as timing and display in the clock, as well as the platform and tools used. The circuit of the digital clock is divided into three modules, namely the frequency division module, counting module, and decoding display module. And the timing process is through the LED display, and the digital tube displays "hours", "minutes", and "seconds" which are displayed in two digits. The frequency division module divides a 50 MHz input signal to obtain a 1 Hz clock signal, and the counting time module can count and adjust the time of the clock, minutes, and seconds, and then display it on the FPGA development board through the decoding display module. After clock simulation, the system realizes the function of the digital clock and meets the design requirements.

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A novel AES-256 implementation on FPGA using co-processor based architecture

Cited by 5 publications

References 9 publications

An Implementation of Configurable and Small- Area AES IP Core Oriented Avalon Bus

An Implementation of Configurable and Small- Area AES IP Core Oriented Avalon Bus

Verilog-based digital clock design methodology

A Review of Design of Digital Clock Based on Verilog HDL

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