A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability

Salahuddin, Shairfe Muhammad; Jiao, Hailong; Kursun, Volkan

doi:10.1109/isqed.2013.6523634

Cited by 48 publications

(19 citation statements)

References 15 publications

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“…SRAM cells designed using asymmetric drain spacer extension FinFETs improve RSNM and WM, and have reduced cell leakage, at the cost of higher access time and area [Goel et al 2011]. SRAM cells designed with asymmetric gate underlap FinFETs can enhance RSNM and writability while reducing leakage power consumption with no area overhead [Salahuddin et al 2013]. Similar to unequally doped FinFETs, FinFETs with asymmetric gate underlap provide unequal current between source and drain for V DS > 0 and V DS < 0 [Goel et al 2011;Salahuddin et al 2013].…”

Section: Related Workmentioning

confidence: 99%

“…SRAM cells designed with asymmetric gate underlap FinFETs can enhance RSNM and writability while reducing leakage power consumption with no area overhead [Salahuddin et al 2013]. Similar to unequally doped FinFETs, FinFETs with asymmetric gate underlap provide unequal current between source and drain for V DS > 0 and V DS < 0 [Goel et al 2011;Salahuddin et al 2013]. In Sachid and Hu [2012], multiple-fin-height FinFETs are used to design denser SRAM cells with better stability and reduced cell leakage.…”

Section: Related Workmentioning

confidence: 99%

“…PGFB is a well-known 6T SRAM cell designed for high read stability [Carlson et al 2010]. It uses IG FinFETs [Salahuddin et al 2013] AUSG AUSG AUSG PGFB [Carlson et al 2010…”

Section: Selection Of Promising Sram Cellsmentioning

confidence: 99%

“…One way to address these problems is to design SRAMs based on FinFETs with asymmetric parameters. SRAM cells based on SPA FinFETs with asymmetry in gate workfunction [Bhoj and Jha 2014], source/drain doping concentration [Moradi et al 2011], gate underlap [Goel et al 2011;Salahuddin et al 2013], and fin height [Sachid and Hu 2012] have been reported. These works have shown that SPA FinFETs can reduce I LEAK , improve stability metrics of the SRAM cell, and help mitigate the SRAM read-write conflict.…”

Section: Introductionmentioning

confidence: 99%

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Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

Guler

Jha

2016

J. Emerg. Technol. Comput. Syst.

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Memory arrays consisting of Static Random Access Memory (SRAM) cells occupy the largest area on chip and are responsible for significant leakage power consumption in modern microprocessors. With the transition from planar Complementary Metal-Oxide-Semiconductor (CMOS) technology to FinFETs, FinFET SRAM design has become important. However, increasing leakage power consumption of FinFETs due to aggressive scaling, width quantization, read-write conflict, and process variations make FinFET SRAM design challenging. In this article, we show how Multiparameter Asymmetric (MPA) FinFETs can be used to design ultra-low-leakage and robust 6T SRAM cells. We combine multiple asymmetries, namely, asymmetry in gate work function, source/drain doping concentration, and gate underlap, to address various SRAM design issues all at once. We propose five novel MPA FinFET SRAM cell designs and compare them with symmetric and Single-Parameter Asymmetric (SPA) FinFET SRAM cells using dc and transient metrics. We show that the leakage current of MPA FinFET SRAM cells can be reduced by up to 58× while ensuring reasonable read/write stability metric values. In addition, high stability metric values can be achieved with 22× leakage current reduction compared to the traditional symmetric FinFET SRAM cell. There is no area overhead associated with MPA FinFET SRAM cells. ACM Reference Format:Abdullah Guler and Niraj K. Jha. 2016. Ultra-low-leakage, robust FinFET SRAM design using multiparameter asymmetric FinFETs.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

“…PGFB is a well-known 6T SRAM cell designed for high read stability [Carlson et al 2010]. It uses IG FinFETs [Salahuddin et al 2013] AUSG AUSG AUSG PGFB [Carlson et al 2010…”

Section: Selection Of Promising Sram Cellsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

Guler

Jha

2016

J. Emerg. Technol. Comput. Syst.

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“…Transistors used in the conventional SRAM cell are symmetrically gate-to-source and gate-to-drain underlapped six FinFETs [17,22,23,[31][32][33]. The symmetrically gate-underlapped FinFETs (FinFET-Sym) are designed and optimized to match the International Technology Roadmap for Semiconductors (ITRS) [5] projections for 15 nm FinFET technology node.…”

Section: Conventional Symmetrical Six-finfet Sram Cellmentioning

confidence: 99%

FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

Salahuddin

Kursun

Jiao³

2015

Transactions on Electrical and Electronic Materials

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Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology. Keywords

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A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications

Sany

Ebrahimi

2021

Circuit Theory & Apps

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Conventional static random‐access memory (SRAM) suffers from high leakage power in advanced complementary metal‐oxide‐semiconductor nodes. Meanwhile, gain‐cell embedded dynamic random‐access memory (GC‐eDRAM) is an area‐efficient alternative to SRAM, although it requires periodic refresh cycles. In this regard, this study proposes a fin field‐effect transistor (FinFET)‐based 5T GC‐eDRAM bitcell that addresses the leakage power issue of SRAM while avoiding the bandwidth‐consuming refreshes of GC‐eDRAM. Furthermore, for the feasibility of scaling down transistors, the gain‐cell design is based on the FinFET, which overcomes short‐channel problems. The proposed 5T bitcell provides additional internal feedback relative to the 4T all‐nMOS fully depleted‐silicon on insulator (FD‐SOI) gain cell to ensure the static retention of both “1” and “0” data. The 2‐kB array was simulated by employing a 7‐nm FinFET predictive technology model (PTM) using HSPICE. The simulation results show that the proposed 5T bitcell (at 0.7 V) enables over 13× smaller data retention power and 10× area reduction compared to the 4T all‐nMOS GC‐eDRAM cell in a 28‐nm FD‐SOI technology.

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A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability

Cited by 48 publications

References 15 publications

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications

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