Proceedings of the 8th IEEE International NEWCAS Conference 2010 2010
DOI: 10.1109/newcas.2010.5603945
|View full text |Cite
|
Sign up to set email alerts
|

A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
4
1

Citation Types

0
23
0

Year Published

2013
2013
2023
2023

Publication Types

Select...
3
2
2

Relationship

0
7

Authors

Journals

citations
Cited by 22 publications
(26 citation statements)
references
References 10 publications
0
23
0
Order By: Relevance
“…In fact, the TDC output code pattern is actual time value which could be floating number rather than binary integral number caused by the calibration and averaging process of the proposed TDC. We can set the bin size or LSB manually [7] with different values which will results in different non-linearity. The non-linearity will be better with bigger LSB setted.…”
Section: Fwhm=214psmentioning
confidence: 99%
See 1 more Smart Citation
“…In fact, the TDC output code pattern is actual time value which could be floating number rather than binary integral number caused by the calibration and averaging process of the proposed TDC. We can set the bin size or LSB manually [7] with different values which will results in different non-linearity. The non-linearity will be better with bigger LSB setted.…”
Section: Fwhm=214psmentioning
confidence: 99%
“…Wang et al make a theoretical analysis of the wave union TDC and present an improved wave union scheme implemented in Xilinx Virtex 4 FPGA [6]. In 2010, M. Daigneault et al proposed a multiple parallel TDLs based TDC architecture, the 24 ps RMS and 10 ps bin size was obtained using 10-parallel TDLs in Virtex II Pro FPGA [7]. In 2011, they also implemented a 10 ps precision TDC using the dynamic reconfiguration function and calibration process in the same FPGA [8].…”
Section: Introductionmentioning
confidence: 99%
“…1 depicts the general structure of a delay-line TDC, see e.g. [3], [14], [16], [17]. The delay-line is tapped in between each two successive delay elements, where each tap drives the data input of an initially enabled latch.…”
Section: Introductionmentioning
confidence: 99%
“…see e.g. [3], [14], [17], time resolution is in the order of 10-80 ps, depending on the used process and inverter structure. With interpolation between delay elements, a bin size of 5 ps has been recently demonstrated, using a 130 nm process [14].…”
Section: Introductionmentioning
confidence: 99%
“…In 2009, the resolution of 55-ps on intervals less than 20-μs was obtained by Aloisio et al [4]. In 2010, a TDC with 24-ps resolution was implemented on Virtex-II Pro FPGA by Daigneault et al [5].…”
Section: Introductionmentioning
confidence: 99%