A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA

Daigneault, Marc-Andre; David, Jean Pierre

doi:10.1109/newcas.2010.5603945

Cited by 22 publications

(26 citation statements)

References 10 publications

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“…In fact, the TDC output code pattern is actual time value which could be floating number rather than binary integral number caused by the calibration and averaging process of the proposed TDC. We can set the bin size or LSB manually [7] with different values which will results in different non-linearity. The non-linearity will be better with bigger LSB setted.…”

Section: Fwhm=214psmentioning

confidence: 99%

“…Wang et al make a theoretical analysis of the wave union TDC and present an improved wave union scheme implemented in Xilinx Virtex 4 FPGA [6]. In 2010, M. Daigneault et al proposed a multiple parallel TDLs based TDC architecture, the 24 ps RMS and 10 ps bin size was obtained using 10-parallel TDLs in Virtex II Pro FPGA [7]. In 2011, they also implemented a 10 ps precision TDC using the dynamic reconfiguration function and calibration process in the same FPGA [8].…”

Section: Introductionmentioning

confidence: 99%

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A multi-chain measurements averaging TDC implemented in a 40 nm FPGA

Shen¹,

Liu²,

Qi³

et al. 2014

2014 19th IEEE-NPSS Real Time Conference

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Abstract-A high precision and high resolution time-to-digital converter (TDC) implemented in a 40 nm fabrication process Virtex-6 FPGA is presented in this paper. The multi-chain measurements averaging architecture is used to overcome the resolution limitation determined by intrinsic cell delay of the plain single tapped-delay chain. The resolution and precision are both improved with this architecture. In such a TDC, the input signal is connected to multiple tapped-delay chains simultaneously (the chain number is M), and there is a fixed delay cell between every two adjacent chains. Each tapped-delay chain is just a plain TDC and should generate a TDC time for a hit input signal, so totally M TDC time values should be got for a hit signal. After averaging, the final TDC time is obtained. A TDC with 3 ps resolution (i.e. bin size) and 6.5 ps precision (i.e. RMS) has been implemented using 8 parallel tapped-delay chains. Meanwhile the plain TDC with single tapped-delay chain yields 24 ps resolution and 18 ps precision.

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Section: Fwhm=214psmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A multi-chain measurements averaging TDC implemented in a 40 nm FPGA

Shen¹,

Liu²,

Qi³

et al. 2014

2014 19th IEEE-NPSS Real Time Conference

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show abstract

“…1 depicts the general structure of a delay-line TDC, see e.g. [3], [14], [16], [17]. The delay-line is tapped in between each two successive delay elements, where each tap drives the data input of an initially enabled latch.…”

Section: Introductionmentioning

confidence: 99%

“…see e.g. [3], [14], [17], time resolution is in the order of 10-80 ps, depending on the used process and inverter structure. With interpolation between delay elements, a bin size of 5 ps has been recently demonstrated, using a 130 nm process [14].…”

Section: Introductionmentioning

confidence: 99%

Metastability-Aware Memory-Efficient Time-to-Digital Converters

Függer

Kinali

Lenzen

et al. 2017

2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

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“…In 2009, the resolution of 55-ps on intervals less than 20-μs was obtained by Aloisio et al [4]. In 2010, a TDC with 24-ps resolution was implemented on Virtex-II Pro FPGA by Daigneault et al [5].…”

Section: Introductionmentioning

confidence: 99%

A Multichannel High-Precision Pulse Counting System Based on FPGA

Zhou

Li³

2015

Proceedings of the Second International Conference on Mechatronics and Automatic Control

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This chapter presents a multichannel and high-precision pulse counting system based on the time interval measurement on the Xilinx ZYNQ-7000 series device. The theoretical resolution of time interval measurement can reach 10-ps using the internal fast carry chain on the field-programmable gate array (FPGA) and the wave union method. As a result, as limited by the hardware condition and the carry chain's structure, the practical resolution of 40-ps is realized, which means that 2048 times subdivision for pulse signal running at 12M is available. It fully meets the requirement of pulse counting in the measurement system of the precise laser interferometer position.

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A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA

Cited by 22 publications

References 10 publications

A multi-chain measurements averaging TDC implemented in a 40 nm FPGA

A multi-chain measurements averaging TDC implemented in a 40 nm FPGA

Metastability-Aware Memory-Efficient Time-to-Digital Converters

A Multichannel High-Precision Pulse Counting System Based on FPGA

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