2014 19th IEEE-NPSS Real Time Conference 2014
DOI: 10.1109/rtc.2014.7097550
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A multi-chain measurements averaging TDC implemented in a 40 nm FPGA

Abstract: Abstract-A high precision and high resolution time-to-digital converter (TDC) implemented in a 40 nm fabrication process Virtex-6 FPGA is presented in this paper. The multi-chain measurements averaging architecture is used to overcome the resolution limitation determined by intrinsic cell delay of the plain single tapped-delay chain. The resolution and precision are both improved with this architecture. In such a TDC, the input signal is connected to multiple tapped-delay chains simultaneously (the chain numbe… Show more

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Cited by 6 publications
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