A Normalization Method for Arithmetic Data-Path Verification

Wedler, Markus; Stoffel, Dominik; Brinkmann, Raik; Kunz, Wolfgang

doi:10.1109/tcad.2007.906458

Cited by 13 publications

(26 citation statements)

References 25 publications

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“…However, this approach is effective when word-level representation is available, which limits their capability in verifying bitlevel implementation. Alternatively, [15] describes a method based on Gröbner bases theory over the ring Z 2 k to verify circuits at arithmetic bit level (ABL) [16]. This paper formulates the verification problem as an equivalent variety subset problem and then conducts a normal form computation.…”

Section: Related Previous Workmentioning

confidence: 99%

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Verification of composite Galois field multipliers over GF ((2m)n) using computer algebra techniques

Kalla

Enescu

2011

2011 IEEE International High Level Design Validation and Test Workshop

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Galois field computations abound in many applications, such as in cryptography, error correction codes, signal processing, among many others. Multiplication usually lies at the core of such Galois field computations, and is one of the most complex operations. Hardware implementations of such multipliers become very expensive. Therefore, there have been efforts to reduce the design complexity by decomposing the Galois field GF(2 k ) as GF ((2 m ) n ) where k = m × n. Such a decomposition introduces a hierarchical abstraction -lifting the ground field from GF (2) (bit-level) to GF (2 m ) (word-level) -thus simplifying the design. This paper addresses the formal verification problem of such multipliers designed over GF ((2 m ) n ), using a computer algebra and algebraic geometry based approach. To prove that the composite field multiplier implementation matches the original specification, we hierarchically formulate the verification problem using the Hilbert's Nullstellensatz over Galois Fields. A Gröbner basis engine is employed as the underlying computational framework. Experiments are performed with various variable/term orders to demonstrate the efficacy of our approach. We can verify the correctness of upto 1024-bit multipliers, whereas SAT/SMT-based approaches are infeasible.

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Section: Related Previous Workmentioning

confidence: 99%

“…For our work, we use the SINGULAR [4] tool. SINGULAR has a restriction that the degree of a variable (q in x q ) be < 2 16 . In cryptography, one encounters very large fields F q where q = 2 256 or higher.…”

Section: B Verification Using Hilbert's Nullstellensatz Over Galois mentioning

confidence: 99%

Verification of composite Galois field multipliers over GF ((2m)n) using computer algebra techniques

Kalla

Enescu

2011

2011 IEEE International High Level Design Validation and Test Workshop

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“…In [4], people have proposed a normalization technique for verifying arithmetic circuits in a bounded model checking environment. Their technique operates on the arithmetic bit level (ABL) description of a given circuit which contains three objects: partial product generator, addition network and comparator.…”

Section: Related Workmentioning

confidence: 99%

“…The second extracted adder calculates P 1 + 8P 4 . As a result the next updated ADD SET will be equal to {P 1 4 , P 2 3 }.…”

Section: Examplementioning

confidence: 99%

“…We use an adder-extraction technique proposed in [3] for equivalence checking of arithmetic circuits based on a Bit-Level Adder (BLA) representation in order to efficiently represent gate-level circuits in HED. This technique benefits from a more efficient reverse engineering process compared to the conventional methods such as arithmetic bit-level (ABL) description in [4]. The BLA directly maps a gate-level description to a word-level addition network, while the ABL is an intermediate representation between gate-level and wordlevel descriptions and further reverse-engineering process is necessary to extract the word-level description from ABL representation.…”

Section: Introductionmentioning

confidence: 99%

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A Unified Framework for Equivalence Verification of Datapath Oriented Applications

Alizadeh

Fujita

2009

IEICE Trans. Inf. & Syst.

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SUMMARYIn this paper, we introduce a unified framework based on a canonical decision diagram called Horner Expansion Diagram (HED) [1] for the purpose of equivalence checking of datapath oriented hardware designs in various design stages from an algorithmic description to the gatelevel implementation. The HED is not only able to represent and manipulate algorithmic specifications in terms of polynomial expressions with modulo equivalence but also express bit level adder (BLA) description of gate-level implementations. Our HED can support modular arithmetic operations over integer rings of the form Z 2 n . The proposed techniques have successfully been applied to equivalence checking on industrial benchmarks. The experimental results on different applications have shown the significant advantages over existing bit-level and also word-level equivalence checking techniques.

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A New Verification Technique for Custom-Designed Components at the Arithmetic Bit Level

Pavlenko

Wedler

Stoffel

et al. 2009

Lecture Notes in Electrical Engineering

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A Normalization Method for Arithmetic Data-Path Verification

Cited by 13 publications

References 25 publications

Verification of composite Galois field multipliers over GF ((2<sup>m</sup>)<sup>n</sup>) using computer algebra techniques

Verification of composite Galois field multipliers over GF ((2<sup>m</sup>)<sup>n</sup>) using computer algebra techniques

A Unified Framework for Equivalence Verification of Datapath Oriented Applications

A New Verification Technique for Custom-Designed Components at the Arithmetic Bit Level

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