A new XOR-based Content Addressable Memory architecture

Frontini, Luca; Shojaii, J.; Stabile, A.; Liberali, V.

doi:10.1109/icecs.2012.6463629

Cited by 25 publications

(10 citation statements)

References 5 publications

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“…The AM-chip is a large digital chip dedicated to real-time pattern recognition using Content Addressable Memory (CAM) architecture [1]. The last version (AM06) has been designed in 65 nm CMOS [2], and employs a CAM cell called ''XORAM'', which combines a conventional 6T SRAM with a XOR gate [3]. The FTK system does not operate close to the particle beam, so radiation tolerance is not required, and the AM chip is not radiation hard.…”

Section: Introductionmentioning

confidence: 99%

An innovative radiation hardened CAM architecture

Anagnostou

Liberali

Mews

et al. 2019

Nuclear Instruments and Methods in Physics Research Section A:

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A B S T R A C TAn innovative Content Addressable Memory (CAM) cell with radiation hardened (RH) architecture is presented. The RH-CAM is designed using a commercial 28 nm CMOS technology. The circuit has been simulated in worstcase conditions, and the effects due to single particles have been analyzed by injecting a current pulse into a circuit node. The proposed architecture is suitable for real-time pattern recognition tasks in harsh environments, such as front-end electronics in the ATLAS experiment at the Large Hadron Collider (LHC) and in space applications.

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Section: Introductionmentioning

confidence: 99%

An innovative radiation hardened CAM architecture

Anagnostou

Liberali

Mews

et al. 2019

Nuclear Instruments and Methods in Physics Research Section A:

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“…An important usage of associative memory are highdensity systems on the chip [2]. The base of these systems are the XOR Associative Memory cells (XORAM cells) on 6-transistor CMOS cells as proposed in [3].…”

Section: Introductionmentioning

confidence: 99%

Evaluation Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory

Katunin

Stenin

2019

MES

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The paper presents TCAD simulation of the 65 nm bulk CMOS logical element of matching, and element of masking based on STG DICE cell with the combinational logic. These items are used for the content addressable memory (associative memory) and the translation lookaside buffers for 65-nm CMOS bulk technology. The combinational logic consists of two tristate inverters (for elements of matching) and additionally consists of two normal inverters (for elements of masking). The STG DICE cell (Spaced Transistor Groups DICE) is different from the standard DICE (Double Interlocked Cell) in that the transistors are separated into two special groups. That is why the charge collection with the tracks of single nuclear particles impacted on one of these groups does not lead to upset of logical state of this memory cell. Failure tolerance of the elements of matching and elements of masking based on the STG DICE cell increases by the separation of its transistors (including the combination logic) into two blocks. Each block consists of one group of transistors of the STG DICE cell and transistors of one of two tristate inverters only for elements of matching and additionally one normal inverter for elements of masking. The charge collection with tracks of nuclear particles was simulated using tracks along the normal to the chip surface. Linear energy transfers were in range 10-60 MeV×cm 2 /mg. The charge collection with tracks onto the linear energy transfer up to 60 MeV×cm 2 /mg does not upset data in STG DICE cells with tracks along the normal to the chip surface. Pulses of error in the output of the combinational logic can occur up to duration 0.3-0.6 ns in the range of the energy transfer 30-60 MeV×cm 2 /mg.

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“…AM05 is an Associative Memory (AM) chip containing 2k patterns based on the XORAM cell [6]. It has been designed in 2014 and it is able to compare patterns with a data rate of 100 MHz.…”

Section: E Associative Memory (Am) Chipmentioning

confidence: 99%

FTK: A hardware real-time track finder for the ATLAS trigger system

Stabile

2016

2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

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Abstract-This paper presents an overview of the ATLAS Fast TracKer (FTK) processor, reporting the design of the system, its expected performance, and the current integration status. The FTK is an upgrade of the trigger system of the ATLAS experiment. The system is designed to reduce the event rate from the proton-proton collisions occurring at 40 MHz to about 1 kHz for the expected LHC luminosity (2×10 34 cm −2 s −1 ). To achieve this selection rate, the FTK system must exploit an intensive use of particle tracking. To this purpose, a dedicated hardware tracker has been designed: the FTK processor. To achieve the required performance, FTK uses a combination of custom VLSI chips and latest generation FPGAs, all embedded in dedicated boards, and it exploits a fully parallel architecture. FTK provides track reconstruction based on the full silicon (inner) detector with resolution comparable to the offline reconstruction with a latency of approximately 100 µs.

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A new XOR-based Content Addressable Memory architecture

Cited by 25 publications

References 5 publications

An innovative radiation hardened CAM architecture

An innovative radiation hardened CAM architecture

Evaluation Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory

FTK: A hardware real-time track finder for the ATLAS trigger system

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