In this paper we propose a novel approach to the synthesis of minimal-sized lattices, based on the decomposition of logic functions. Since the decomposition allows to obtain circuits with a smaller area, our idea is to decompose Boolean functions with separate lattices, according to the P-circuits decomposition scheme, and then to implement the decomposed blocks with physically separated regions in a single lattice. Experimental results show that about 35% of the considered benchmarks achieve a smaller area when implemented using the proposed decomposition for switching lattices, with an average gain of at least 24%

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This paper describes the AM06 chip, which is a highly parallel processor for pattern 15 recognition in high energy physics experiments. It contains memory banks that store data organized 16 in 18 bit words; a group of 8 words is called "pattern". Each AM06 chip can store up to 2 17 patterns. 17The AM06 integrates serializer/deserializer IP blocks at 2 Gbit/s for input/output communication,

Abstract-We describe an important advancement for the Associative Memory device (AM). The AM is a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture. The AM is optimized for on-line track finding in high-energy physics experiments. Pattern matching is carried out by finding track candidates in coarse resolution "roads". A large AM bank stores all trajectories of interest, called "patterns", for a given detector resolution. The AM extracts roads compatible with a given event during detector read-out.Two important variables characterize the quality of the AM bank: its "coverage" and the level of fake roads. The coverage, which describes the geometric efficiency of a bank, is defined as the fraction of tracks that match at least one pattern in the bank. Given a certain road size, the coverage of the bank can be increased just adding patterns to the bank, while the number of fakes unfortunately is roughly proportional to the number of patterns in the bank. Moreover, as the luminosity increases, the fake rate increases rapidly because of the increased silicon occupancy. To counter that, we must reduce the width of our roads. If we decrease the road width using the current technology, the system will become very large and extremely expensive.We propose an elegant solution to this problem: the "variable resolution patterns". Each pattern and each detector layer within a pattern will be able to use the optimal width, but we will use a "don't care" feature (inspired from ternary CAMs) to increase the width when that is more appropriate. In other words we can use patterns of variable shape.As a result we reduce the number of fake roads, while keeping the efficiency high and avoiding excessive bank size due to the reduced width.We describe the idea, the implementation in the new AM design and the implementation of the algorithm in the simulation. Finally we show the effectiveness of the "variable resolution patterns" idea using simulated high occupancy events in the ATLAS detector.

Pixel detectors at HL-LHC experiments or other future experiments are facing new challenges, especially in terms of unprecedented levels of radiation and particle flux. This paper describes the progress made by the CHIPIX65 project of INFN for the development of a new generation readout ASIC using CMOS 65 nm technology.