A new VLSI vector arithmetic coprocessor for the PC

Baumhof, C.

doi:10.1109/arith.1995.465356

Cited by 7 publications

(4 citation statements)

References 3 publications

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“…An exactly rounded result can be obtained using a hardware approach, but this is usually realized at the expense of a very large internal mantissa [Baumhof 1995;Kulisch 2002;Tenca 2009]. Low error bounds can be guaranteed by a topological approach.…”

Section: Hardware Summationmentioning

confidence: 99%

Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators

Ould-Bachir

David

2013

ACM Trans. Reconfigurable Technol. Syst.

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Advances in semiconductor technology brings to the market incredibly dense devices, capable of handling tens to hundreds floating-point operators on a single chip; so do the latest field programmable gate arrays (FPGAs). In order to alleviate the complexity of resorting to these devices in computationally intensive applications, this article proposes hardware schemes for the realization of addition-related floating-point operators based on the self-alignment technique (SAT). The article demonstrates that the schemes guarantee an accuracy as if summation was computed accurately in the precision of operator's internal mantissa, then faithfully rounded to working precision. To achieve such performance, the article adopts the redundant high radix carry-save (HRCS) format for the rapid addition of wide mantissas. Implementation results show that combining the SAT and the HRCS format allows the implementation of complex operators with reduced area and latency, more so when a fused-path approach is adopted. The article also proposes a new hardware operator for performing endomorphic HRCS additions and presents a new technique for speeding up the conversion from the redundant HRCS to a conventional binary format.

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Section: Hardware Summationmentioning

confidence: 99%

Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators

Ould-Bachir

David

2013

ACM Trans. Reconfigurable Technol. Syst.

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“…The implementation of the long accumulator is similar to the one presented in [2,19]. It functions as an extremely long fixed point register and is useful for performing variable-precision arithmetic operations without roundoff error or overflow.…”

Section: Hardware Designmentioning

confidence: 99%

“…To improve the accuracy and performance of vector and matrix operations, processors that support exact dot products have been designed [2,13,19]. To improve the accuracy and performance of vector and matrix operations, processors that support exact dot products have been designed [2,13,19].…”

Section: Introductionmentioning

confidence: 99%

Variable-precision, interval arithmetic coprocessors

Schulte

Swartzlander

1996

Reliable Comput

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This paper presents hardware d~igns, arithmetic algorithms, and numerical applicmions for variableprecision, interv:il arithmetk coproces.~rs. These copr~mes.,~ms give the programmer the ability to ~ the initial precision of the comptttation, determine the accuracy of the results, and recomput¢ inaccttrate r~ults with higher precision. Variable-precision, interval arithmetic algorithms are used to reduce the execution times of numeric,'al applications. Three hardware designs with data "paths of 16, 3, 9, and 64 bits are examined. These designs are compared based tm their estimated chip area, cycle time, and executi~m times for various numerical appliGltinns. ~lch copl'~es.~r call be inlp[elnentorl on a single chip with a cycle time th:~t is comparable to IEEE double-precision floating point coprocessors. For certain numerical appficatkms, the copr~:es.,~rs ;ire two to |i~tlr orders of magnitude faster than *1 collventiotla] .,~)ftwar¢ package fi~r variable-precision, interval arithmetic. JAHTepBaAt I-IIIe apt@MeTtl iecKI/ie conpoIIeccopbI riepeMeHHOfi pa3p AHOCT M. FI. I~YAbTE t E. E. I~APLIAAI-L&EP, MA. rlpe;lcTaBaem,t gOHcTpygRtta almapaTyphL tlCIIO:lb3yeMble apttqbxterHqecgtte a:wopt~rMbt }t HpttJm~Ke-HtlH K pelueHlllo ql|CJIeHHNIX 3~t;'laq JlflH ltHTepl~l'IbHblX aptil~bMeTllqeCKttX Ct~|Ip~lleC.CoIX~B ltepeMeHHof! pa3pmmtw:rtt, [')vn cotlpoileccopm IIt)3Bt).'IHR)T IIpol'paMMItCTy yCT;IHaBdlIIIGITb t~atta.'~f, Hys~ pa3pHltHocrb Bt~Iq|I(Z'IeHIII~f, ()llp~/tCdlHTb TOqHOCTb pe3ydlbT~rroB tt 31tHOIR) Bl~'4ItG1~rrb FleToqHbl~ pe'3y,'Ib~tTbI C ~)dlb|l|~(! pa3p/.121ttOCTl,lo. ;~'l~I yMeHblIIeHtlH BpeMeHH BIMIIOJIHCHIIH B qllC'leHHhtX IlplL'lo)KeHtt.qX llCll{Plb3ylo'rC/-I IIHTepBIIdlbHO-aptICI~MeTItqecKHe ;I)IFOp~ITM,-I llepeMeHHOt~ pa3p~aHOCTIt. PaCCMOTpeHbt TpJI allll;lpaTHl, le CXeMI,I C tllllm)~t naHHlaX IttttpttHO~ 16, 3 9 I4 64 6ItTa. 2-)Tit CxeMla cpaBHHBag~TC~I llo wpe6yeMofi Itaolita.3.tl Kp}tcra.'Idla, ltp~/tOdlt~HTe.'IbUOCTtI pafxmero IIHK,|;I lt! i~MCTpOJ|elTICTB||R) B pa3altqHMx qtic'leH-HblX IIp|I:tOIKeHIII4X. Ka.q3KMf! IE~ ~TIIX C(}IIpOIIeccoI~t~B Mt}gKeT 6MTb |)e;Lqlti3oB~lH Wd OjtHt)M gptiCT~l$1.'lt~ C pa&~qefl H,'tCTOTOlTI, CpRBH~IMOft C COIIpoIleCcopaMH Hdlill~ll¢)IIIel4 TOt~KH "tBOfIHO~ TOtlH(~Ttl craHaap'ra IEEE. B HegoTOpblX qltC.'IeHHbIX ]IpHJIOTK¢~HH.o2X HalllI! COilpOt[eccopM Ha 2[B~t-qeTMpe IlOp.'4/lga 6McTpee, qeM pacrtt~c'rpaf~eHnbm IlpOl'paMMHbl¢ ItaKeThI, pe~l'lIl3yl(Hlllie ;lHTepBaJlbHy~ aptl010Me'rttKy llepeMeHHo/'t pa3p~anoc'rtt.

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“…Hardware implementations help overcome the speed disadvantage of software realizations [13]. Previous research in this area includes the design of accurate dot product processors [20], [21], functional units for rational arithmetic [22], variable-precision integer processors [23], and variable-precision floating point processors [24]. Although these processors help improve the accuracy of the computation, they do not provide an efficient method to determine how accurate the results are.…”

Section: Introductionmentioning

confidence: 99%

A family of variable-precision interval arithmetic processors

Schulte

Swartzlander

2000

IEEE Trans. Comput.

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ÐTraditional computer systems often suffer from roundoff error and catastrophic cancellation in floating point computations. These systems produce apparently high precision results with little or no indication of the accuracy. This paper presents hardware designs, arithmetic algorithms, and software support for a family of variable-precision, interval arithmetic processors. These processors give the programmer the ability to detect and, if desired, to correct implicit errors in finite precision numerical computations. They also provide the ability to solve problems that cannot be solved efficiently using traditional floating point computations. Execution time estimates indicate that these processors are two to three orders of magnitude faster than software packages that provide similar functionality.

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A new VLSI vector arithmetic coprocessor for the PC

Cited by 7 publications

References 3 publications

Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators

Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators

Variable-precision, interval arithmetic coprocessors

A family of variable-precision interval arithmetic processors

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