A New Variable Frequency Control of 49-Level Cascaded Packed U-Cell Voltage Source Inverter

Meraj, Mohammad; Rahman, Syed; Iqbal, Atif; Tariq, Mohd; Lodi, Kaif Ahmed; Ben‐Brahim, Lazhar

doi:10.1109/tia.2019.2941171

Cited by 31 publications

(14 citation statements)

References 32 publications

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“…A 49-level PUC is reported in [151,152] by cascading two asymmetrical seven-level PUC units demonstrates the asymmetric ability of PUC. A ZPUC converter is reported in [153] to operate PUC with a single dc-link for both single-phase and three-phase systems.…”

Section: Topologies With Ladder-based Structuresmentioning

confidence: 95%

A Survey on Reduced Switch Count Multilevel Inverters

Vemuganti¹,

Sreenivasarao

Ganjikunta

et al. 2021

IEEE Open J. Ind. Electron. Soc.

103

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An efficient and cost-effective power converter is a pre-requisite for the modern power applications. With the evolvement of matured medium power self-commutated switching devices, multilevel inverters (MLIs) are emerged as a promising solution for high-power medium-voltage applications. Though, MLIs are performing a promising role in industrial applications, their high device count, size, cost and control complexity have restricted their market penetration. To address the disadvantages of MLIs, researchers are continuously contributing to new generation topologies under the name of reduced switch count (RSC) MLIs. From the past decade, numerous RSC-MLIs topologies have been reported for various applications. Therefore, this paper presents a comprehensive review and classification of RSC-MLI topologies, in terms of their structure, features, limitations, suitability and selection for specific applications..

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Section: Topologies With Ladder-based Structuresmentioning

confidence: 95%

A Survey on Reduced Switch Count Multilevel Inverters

Vemuganti¹,

Sreenivasarao

Ganjikunta

et al. 2021

IEEE Open J. Ind. Electron. Soc.

103

View full text Add to dashboard Cite

show abstract

“…Using (10) and (11), the switching angles with optimisation are calculated using the particle swarm optimisation (PSO)-based algorithms explained in [39]. For the proposed 11-level topology, the variation of optimised switching angles (θ 1 , θ 2 , …, θ 5 ) with respect to the modulation index depicted in Fig.…”

Section: Modulation Techniquementioning

confidence: 99%

“…One class of multilevel inverters has been packed U-cell (PUC) [9][10][11][12][13][14]. In PUC converters, the lack of boosting ability has been the main limitation of these converters for high-voltage applications.…”

Section: Introductionmentioning

confidence: 99%

Dual input switched‐capacitor‐based single‐phase hybrid boost multilevel inverter topology with reduced number of components

Rawa

Siddique

Mekhilef

et al. 2020

IET Power Electronics

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A new switched-capacitor-based topology with features of boosting and self-voltage balancing of the capacitor has been proposed in this study. The proposed multilevel inverter topology uses two isolated dc voltage sources with a switchedcapacitor to produce 11 levels across the load. In this study, two different modes of the selection of dc voltage sources have been discussed for the proposed topology. Furthermore, the generalised structure of the proposed boost topology has also been discussed. Quantitative comparison with several topologies has been carried out to set the benchmark of the proposed topology. Selective harmonic elimination pulse width modulation technique has been adopted to improve the performance of the suggested topology. The power loss analysis of the proposed topology gives the maximum efficiency of 96.5% at the output power of 100 W and has an efficiency value of 95.3% at the output power of 500 W. The proposed topology has been simulated using PLECS and the simulation results have been verifying using an experimental prototype. The proposed topology has been tested for the different types of load and changes in the modulation index. The experimental results have verified the feasibility of the proposed topology.

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“…This cascading operation requires 4 DC source and produces 31-level output. Recently, a 49-level AMLI was proposed by cascading two PUCs [20], in which two asymmetrical batteries and two capacitors were employed. These 49 levels were achieved by employment of 2 DC sources and 12 IGBTs only.…”

Section: Introductionmentioning

confidence: 99%

Modulation With Metaheuristic Approach for Cascaded-MPUC49 Asymmetrical Inverter With Boosted Output

et al. 2020

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This work introduces a 49-level Asymmetrical Inverter (AMLI) with boosted output based on the cascaded operation of two 7-Level Modified Packed U-Cell inverters (MPUC-7). The converter is capable of operation with a boosted voltage of up to 1.714 times the maximum DC voltage employed. It requires only 12 active switches and 4 voltage sources. With the sources set in the ratio of 14 : 7 : 2 : 1, the 7-level output of the two converters is so utilized that the 7 2 = 49-level output voltage is generated across the load. A detailed explanation of level formation is discussed. This converter is operated using an Artificial Neural Network (ANN) which is trained for the harmonic elimination in the output voltage waveform. For the calculation of optimum angles, a meta-heuristic based Genetic Algorithm (GA) technique is employed. The generation of 49-level output requires 24 transitions in one quarter of a cycle. All these angles are generated for various desired output voltages, and the ANN is trained offline for the same. The converter and its control are simulated in MATLAB/Simulink environment, and the results are verified on the experimental setup. The multilevel output thus obtained is nearly sinusoidal and the Total Harmonic Distortion (THD) thus produced is under the specified limit of IEEE.

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A New Variable Frequency Control of 49-Level Cascaded Packed U-Cell Voltage Source Inverter

Cited by 31 publications

References 32 publications

A Survey on Reduced Switch Count Multilevel Inverters

A Survey on Reduced Switch Count Multilevel Inverters

Dual input switched‐capacitor‐based single‐phase hybrid boost multilevel inverter topology with reduced number of components

Modulation With Metaheuristic Approach for Cascaded-MPUC49 Asymmetrical Inverter With Boosted Output

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