A New Test Point Selection Method for Analog Continuous Parameter Fault

Luo, Hui; Lü, Wei; Wang, Youren

doi:10.1007/s10836-017-5661-1

Cited by 10 publications

(3 citation statements)

References 22 publications

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“…The importance of printed circuit board (PCB) testing adds a role with the design for testability (DFT) techniques, merged from the beginning phase of design to reduce the testing cost and test application time. The main aim of testing is to detect the target faults and locate the place of their occurrence [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

New Board-Level Interconnect Fault Diagnosis Approach in Industrial Applications

Aziz¹,

El-Mahlawy²

2021

IJCDS

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In this paper, the new BIST approach to test interconnect faults, based on the boundary scan architecture, is presented. The new algorithm is implemented by the MATLAB code, whose analysis is based on the random manner to generate the required test pattern set that detects interconnect faults without aliasing and confounding syndromes. The test pattern set complies with all requirements to detect two and three short-circuits from seven and ten terminals of ICs (boards). Different test responses of each short-circuit between different terminals are achieved, considered the basis of the presented fault diagnosis approach. In addition, this paper presents two generative approaches that generate the target test set. It is found that one generative approach using a linear feedback shift-register (LFSR) and a decoder reduces the test application time and suffers from aliasing and confounding syndromes due to the multi-input shift-register (MISR) with high hardware overhead. However, the other generative approach using an LFSR only has large test application time and is not suffering from aliasing and confounding syndromes with low hardware overhead. The new algorithm is compared with several previously published algorithms. The simulation results of the new algorithm have best results comparing to the existing algorithms in terms of the fault coverage and the applicability of the BIST scheme. The new algorithm is the most efficient algorithm to diagnose interconnect faults, based on two and three short-circuits from seven and ten terminals of ICs with accepted test application time and without aliasing and confounding syndromes.

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Section: Introductionmentioning

confidence: 99%

New Board-Level Interconnect Fault Diagnosis Approach in Industrial Applications

Aziz¹,

El-Mahlawy²

2021

IJCDS

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“…Zhang [2], Meng [3] and Li [4] studied test point selection. Khanlari [5], Saeedi [6], Tang [7], Cui [8] and Luo [9] researched the test point selection approach for analog circuits. Sensor selection is a further refinement of test selection.…”

Section: Introductionmentioning

confidence: 99%

System level test selection based on combinatorial dependency matrix

Yang

Xie²,

Qiu

2021

J. of Syst. Eng. Electron.

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Test selection is to select the test set with the least total cost or the least total number from the alternative test set on the premise of meeting the required testability indicators. The existing models and methods are not suitable for system level test selection. The first problem is the lack of detailed data of the units' fault set and the test set, which makes it impossible to establish a traditional dependency matrix for the system level. The second problem is that the system level fault detection rate and the fault isolation rate (referred to as "two rates") are not enough to describe the fault diagnostic ability of the system level tests. An innovative dependency matrix (called combinatorial dependency matrix) composed of three submatrices is presented. The first problem is solved by simplifying the submatrix between the units' fault and the test, and the second problem is solved by establishing the system level fault detection rate, the fault isolation rate and the integrated fault detection rate (referred to as "three rates") based on the new matrix. The mathematical model of the system level test selection problem is constructed, and the binary genetic algorithm is applied to solve the problem, which achieves the goal of system level test selection.

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“…In [11,19,35], there are the techniques that use support vector machines for faults detection. Heuristic computations and statistical analysis are used in [4,[6][7][8]13,18,20] for catastrophic and global parametric faults detection as well as for optimal test points and testing signal shape searching, respectively. In [34], the entropy parameter is used to analog circuit soft faults detections.…”

Section: Introductionmentioning

confidence: 99%

Analog Circuit Specification Testing by Means of Walsh–Hadamard Transform and Multiple Regression Supported by Evolutionary Computations

Golonek

Machniewski

2017

Circuits Syst Signal Process

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This paper describes an approach for an analog electronic circuit specification quick verification that is based on a simple mathematical model determined during the before-test stage statistical analysis. Generally, the observed performance parameters (e.g., cutoff frequency, phase shift at the assumed frequency point) are calculated from the Walsh-Hadamard transform components of circuit under test step time response. The optimal estimating formulas for relationship between the tested specifications and the selected components of the spectra are defined in the system based on a linear multiple regression procedure supported by genetic programming. The evolutionary computations significantly improve the approximation effectiveness by selecting the most representative points of the sequences domain and by defining the optimal set of linearizing functions. Finally, at the test stage, only a simple step stimulus and time-effective calculations are required to the tested performance parameters (specifications) of analog circuit identification and it predisposes the approach to quick production testing procedure realization or to embedding it in the mixed-signal systems. The automated built-in self-testing procedure using this concept may be easily implemented to low-cost microcontroller equipped with AD converter used for the testing response samples acquiring.

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A New Test Point Selection Method for Analog Continuous Parameter Fault

Cited by 10 publications

References 22 publications

New Board-Level Interconnect Fault Diagnosis Approach in Industrial Applications

New Board-Level Interconnect Fault Diagnosis Approach in Industrial Applications

System level test selection based on combinatorial dependency matrix

Analog Circuit Specification Testing by Means of Walsh–Hadamard Transform and Multiple Regression Supported by Evolutionary Computations

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