A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles

Abstract

In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of flash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N it) and oxide trap charges (Q ox) under both channel-hot-electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N it and Q ox. Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay, and we found that the interface state generation is the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read-disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes.

Relaxation-free characterization of Flash programming dynamics along P-E cycling

“…Figure 7 shows Ifg(t) data plotted as a function of Vfg(t) during PROG: they exhibit a continuous stretch along cycling, which is described thanks to an exponential fit factor . From [8], this behavior is attributed to Coulomb scattering effects linked with HC-induced interface traps (Dit) near the drain. Further investigation will consist in correlating electrical signatures of interface traps both during PROG (saturation regime, as in Figure 7) and during READ operations [9] (linear regime).…”

Characterization of hot-hole injection induced SILC and related disturbs in flash memories

“…and represent the length of damage region and the depth of generated oxide traps above the Si/SiO interface. The value of can be extracted from the gated-diode measurement technique that we developed in [20] (e.g., Fig. 9), where value of m is used.…”

Principles of Floating Gate Devices

“…Detrimental effects of hot-electrons (namely: drain current reduction, small signal performance degradation, threshold voltage shift and I D sub-threshold slope lowering) are due to both interface state generation and the charge trapping in the portion of oxide above the drain junction. Thus, to gain insights into degradation of both MOS performances [7][8][9] and Flash memory cell reliability [10][11] hot carrier phenomena have been studied through experimental techniques. Moreover, the CHE current has been studied also by means of models developed to reproduce real features of the phenomenon.…”