A new successive approximation architecture for high-speed low-power ADCs

A 2-bit/step SAR ADC structure with one radix-4 DAC

“…We expect from our proposed design that due to using half resolution small DAC with lower mismatch errors, the linearity parameters INL and DNL are be improved but offset difference of three comparators can create some mismatches which affected on proposed ADC linearity parameters. It is a common problem in the presented works for 2-bit/step algorithm based design in [1,2,3]. However, the achieved static linearity parameters are −0.8LSB < INL < 1.5LSB and −1LSB < DNL < +0.99LSB which shows in Fig.…”

“…Therefore, in the comparison with other works [1,2,3,4], our proposed 2-bit/step SAR ADC structure hast more compact structure, because it used only "one DAC" with "radix-4" with "half resolution" and small control logic unit with N/2 flip-flops less than conventional architecture and in the other side, its Reference Generator is "resolution independent" and its transistor counts will be constant for all resolution range.…”

“…The previous 2-bit/step designs [1,3] have two or more full-scaled internal DACs, while the proposed SAR ADC comes with one simple N/2-bit radix-4 DAC as modeled in Fig. 1 (b).…”

“…It may increase the speed of ADC by factor M, but 2 M − 1 comparators are required, which causes to increase on the chip area and power consumption for M > 3 and degrade the linearity of ADC due to comparators offset and mismatch. The recent approach is the resolving two bits in each clock cycle in SAR ADC conversion procedure [1,2,3,4]; thereby the conversion rate of SAR ADC by this solution is increased two times faster. The main drawbacks of the known [1,2,3,4] 2-bit/step SAR ADC are the big and complex structures with several DAC networks in [1,2] and multiplexers in [3] or the thermal noise and process variation sensitive comparators design in [4], which limits them to only low-bit resolution applications.…”

A fully integrated RSSI and an ultra-low power SAR ADC for 5.8 GHz DSRC ETC transceiver

“…It is reported [17] that synchronous logic control for the ADCs is not power efficient. The design in [20] achieves a sampling rate of 40MS/s with doubled power consumption. Therefore, asynchronous operation of comparators gets rid of a high-frequency clock and greatly improves the power efficiency [17].…”