High-speed and low-power scalable Hamming weight comparator based on a non-weighted switched-capacitor array

Abdel-Hafeez, Saleh; Parhami, Behrooz

doi:10.1007/s10470-012-9991-8

Cited by 3 publications

(3 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A good example is in circuits that compare Hamming weights of two different sequences or the weight of one sequence against a fixed threshold [20]. Unfortunately, however, circuit realization through switched-capacitor array usually implies high design cost and large power consumption due to the need for a high-resolution analog comparator.…”

Section: Basic Concepts and Functionalitymentioning

confidence: 99%

“…More details on reducing the mismatches between capacitances in switched-capacitor arrays can be found in several of our references [19,20,[36][37][38]. Analysis results show that the worst-case capacitance mismatches are such that the layout can support N = 64 or higher, with mismatch error not exceeding 22 %, while providing a resolution on the order of 8 mV.…”

Section: Assessment Via Hspice Simulationmentioning

confidence: 99%

“…Many circuits in the latter class have been designed to cater to specific applications or application domains involving Hamming vectors and weights. Among the many available options, one finds all-digital designs [9][10][11][12], digital designs based on the technology-ratioed approach [13][14][15], designs using lookup tables and approximations [16][17][18], and, in the case of our prior contributions, mixed digital-analog designs that are more compact and use highspeed parallel evaluation [19,20]. A general view, covering both radix-based weights and unit weights, is the assignment of arbitrary ''importance'' to various features [21].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A mixed analog–digital fast hamming-weight filtering circuit using switched-capacitor arrays

Abdel-Hafeez

Parhami

Alhammouri

2015

Analog Integr Circ Sig Process

Self Cite

View full text Add to dashboard Cite

Many circuit design applications rely on an intermediate sequence to carry a decision to the next circuit stage. The decision may be carried by a weighted pattern of N bits, with the weights being selected in a way that optimizes the circuit implementation or some aspect of performance. For example, when the weights are consecutive powers of 2 beginning with 1 = 2 0 , we have the standard binary representation. As another example, when all the weights are 1, we have the unary representation that encodes a value k by k asserted bits and N-k unasserted bits (a weightk bit vector of length N). In this paper, we present the design of a circuit that screens a unary representation to verify that the represented value falls between preset lower and upper limits l and u, passing through any string that represents a value in the interval [l, u] and outputting the all-0 s bit pattern otherwise. Our mixed analog-digital circuit implementation, based on switched-capacitor arrays, provides a decision output within a clock cycle of 4 ns for 16-bit unary representation, when realized with 0.15 lm TSMC technology. The latter results were obtained with normal, per-bit capacitance of 200 fF and single-clock-cycle operation. As an added benefit, our filtering circuit can form the basis for designing a cost-effective Hamming decoder circuit.

show abstract

Section: Basic Concepts and Functionalitymentioning

confidence: 99%

Section: Assessment Via Hspice Simulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A mixed analog–digital fast hamming-weight filtering circuit using switched-capacitor arrays

Abdel-Hafeez

Parhami

Alhammouri

2015

Analog Integr Circ Sig Process

Self Cite

View full text Add to dashboard Cite

show abstract

In‐Memory Hamming Weight Calculation in a 1T1R Memristive Array

Cheng

Zheng

et al. 2020

Adv Elect Materials

View full text Add to dashboard Cite

In‐memory computing enabled by advanced nonvolatile memory technologies, such as memristors and memristive devices, emerges as a promising approach to accelerate certain data‐intensive algorithms, and thus outperforms the von Neumann computing in terms of processing latency and energy efficiency. In this work, an efficient method to calculate the Hamming weight (HW) of a binary string in a one‐transistor‐one‐resistor (1T1R) memristive array is proposed, which can be beneficial for various computation tasks. Specifically, the target string is converted to a voltage vector and multiplies with an “all‐1” string pre‐stored in the resistance of the row, which equals to a binary matrix multiplication or AND logic operation. The in situ stored HW calculation result is then read out through a current accumulation operation. As a proof‐of‐concept demonstration, 4 bit and 8 bit HW calculation is successfully implemented in experiment and simulation, respectively. In addition, the influence of the resistance variation on the calculation correctness is discussed. This work broadens the application range of using emerging nonvolatile memories for classical information processing in hardware level with high efficiency.

show abstract

Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators

Vergos

Bakalis

Anastasiou

2014

Circuits Syst Signal Process

View full text Add to dashboard Cite

High-speed and low-power scalable Hamming weight comparator based on a non-weighted switched-capacitor array

Cited by 3 publications

References 23 publications

A mixed analog–digital fast hamming-weight filtering circuit using switched-capacitor arrays

A mixed analog–digital fast hamming-weight filtering circuit using switched-capacitor arrays

In‐Memory Hamming Weight Calculation in a 1T1R Memristive Array

Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators

Contact Info

Product

Resources

About