2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) 2017
DOI: 10.23919/ispsd.2017.7988895
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A new sub-micron trench cell concept in ultrathin wafer technology for next generation 1200 V IGBTs

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Cited by 34 publications
(26 citation statements)
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“…The wafer thicknesses of devices have been approaching to the theoretical limits for the rated voltage class. A latest trend of the ndrift design is towards higher resistivity and thinner thickness in order to ensure both high blocking capability and low overall loss [32]. Our approach for a deep n-buffer structure is the introduction of Controlling charge carrier Plasma Layer (CPL) ( Fig.…”
Section: Improving Usabilitymentioning
confidence: 99%
“…The wafer thicknesses of devices have been approaching to the theoretical limits for the rated voltage class. A latest trend of the ndrift design is towards higher resistivity and thinner thickness in order to ensure both high blocking capability and low overall loss [32]. Our approach for a deep n-buffer structure is the introduction of Controlling charge carrier Plasma Layer (CPL) ( Fig.…”
Section: Improving Usabilitymentioning
confidence: 99%
“…This effect increases the drift region cathode side carrier concentration and enables a p-i-n diode like carrier profile. The same effect is used in 1D scaling of mesa width [6], 2D and 3D scaling of cathode cells [3,4] as well as deep sub-micron designs [7]. However, the IE effect also results in non-saturation of the MOS channel current, leading to significant degradation of short circuit withstand capability [8,9].…”
Section: Recommended For Publication By Associate Editormentioning
confidence: 99%
“…Different approaches have been suggested in the literature (e.g. [7][8][9][10][11][12][13]). A very promising approach is the MPT concept with sub-µm mesa widths to increase the carrier confinement and increased channel width to further lower the on-state voltage.…”
Section: Advanced Concepts For Power-loss Reductionmentioning
confidence: 99%