A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-Type) 3-D NAND

Yeh, Teng-Hao; Wu, Chao-I; Hu, Chih‐Wei; Chen, Wei‐Chen; Lue, Hang-Ting; Shih, Yung‐Feng; King, Ya‐Chin; Lu, Chih‐Yuan

doi:10.1109/led.2015.2399107

Cited by 5 publications

(8 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For VG 3D NAND, the formation of the strings is quite straightforward; the wordline and sourceline resistance is managed easily, however the connection to the bitline and the string selection is more complicated compared to vertical channel. In [29,30] a simple method for SSL transistor formation is proposed; this is a special connecting structure from the horizontal polysilicon string channels to the metal bitlines, and it optimizes the layout of the select transistors. Figure 11.…”

Section: Vertical Gate-type Architecturesmentioning

confidence: 99%

See 1 more Smart Citation

3D NAND Flash Based on Planar Cells

Silvagni¹

2017

Computers

View full text Add to dashboard Cite

Abstract:In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a "punch-and-plug" process-with gate-all-around (GAA) cell devices-against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production.

show abstract

Section: Vertical Gate-type Architecturesmentioning

confidence: 99%

“…A split-gate architecture was also proposed in order to relax the lithography on the select gates (split-gate architecture). Several other innovations have led to a very compact layout of the VG NAND and its operation [29][30][31][32].…”

Section: Single-gate Vertical Channel (Sgvc) Architecturementioning

confidence: 99%

3D NAND Flash Based on Planar Cells

Silvagni¹

2017

Computers

View full text Add to dashboard Cite

show abstract

“…Other approaches for the layer selector scheme and SSL arrangement have also been proposed: PN diode selection method [19] and staggered SSL arrangement [26]. In particular, the proposed staggered SSL arrangement allows achieving a block efficiency of 80 %, which is similar to that of 2D NAND.…”

Section: Vg-type 3d Nand Architecturementioning

confidence: 99%

“…The figure shows a structure having two basic units Fig. 7.15 Optimization of split-page string decoding in 3D-VG-Type NAND [26] side by side. Each unit is composed of four strings for each layer.…”

Section: Vg-type 3d Nand Array Operationsmentioning

confidence: 99%

3D VG-Type NAND Flash Memories

Silvagni

2016

3D Flash Memories

View full text Add to dashboard Cite

Solid State Disk applications have been the main drivers for the cost reduction of NAND Flash memory. Technology scaling limits have been almost reached and new directions were investigated for a decade. 3D NAND appeared as the most promising and short term viable solution to the scaling problem. 3D NAND offers the possibility to keep scaling memory density beyond 2D NAND 1z nm technology and opens new landscapes if the technology hurdles can be definitely overcome. Additionally Multi bit per cell technology is applicable to 3D NAND as well; therefore, the storage capacity growth trend is not going to meet the inflection point soon. Big Data storage demand remains certainly the driver for the rapidity of 3D NAND to become industry mainstream.With respect to the flat 2D NAND Flash, three-dimensional architectures demand a more challenging approach to deal with process, design architectures, parasitic effects, testing. At the time of writing this chapter, 3D technology is moving into production inside solid state storage solutions; however, those NAND chips aren't commercially available as raw components. 3D NAND chips are used by vertically integrated manufacturers and few partners to build the storage systems under a strict control on the usage. Technology solutions are still diversified among the few players in the 3D arena and no unique mainstream solution is emerged yet.In this chapter the principal architectural pieces of 3D NAND will be reviewed putting the focus on one of them: VG-Type, Vertical Gate 3D NAND.

show abstract

“…Recently, three-dimensional (3D) stack NAND flash memories such as SMArT, 1,2) P-BiCS, [3][4][5][6] TCAT 7,8) and vertical gate, [9][10][11] which consists of the thin film polysilicon (poly-Si) channel [12][13][14] have been introduced to be the most promising near-term solution to over-come scaling challenges in conventional planar NAND flash memories. [15][16][17][18][19][20] However, as 3D vertical-NAND (V-NAND) flash memories shrink nonideal characteristics and performance degradation of the memory have been consistently reported.…”

Section: Introductionmentioning

confidence: 99%

Improvement of cell characteristics using controlling the current path in 3D NAND flash

Park

Lee

CHO

et al. 2023

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

In vertical-NAND (V-NAND) flash memory, the effect of current path change according to the program state was analyzed. A new memory structure in which a heavily doped polysilicon layer is added around a typical V-NAND channel was proposed, and electrical characteristics were observed through simulation. As a result, it was confirmed that the electrical characteristics such as Vth and S.S of V-NAND can be changed and that the current path can be adjusted. Through an experiment to change the doping concentration of the added doping area, there was a sudden change in the current path at 5.0  1017/cm3and 5.2  1017/cm3during boron doping. The change of the current path was observed at this rapidly changing point, and the device characteristics could be dramatically improved if the current path was changed by adding an extra doping region. Additionally, the effects of program operating voltage conditions and doping type changes on V-NAND operation were analyzed.

show abstract

A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-Type) 3-D NAND

Cited by 5 publications

References 6 publications

3D NAND Flash Based on Planar Cells

3D NAND Flash Based on Planar Cells

3D VG-Type NAND Flash Memories

Improvement of cell characteristics using controlling the current path in 3D NAND flash

Contact Info

Product

Resources

About