2016 IEEE International Electron Devices Meeting (IEDM) 2016
DOI: 10.1109/iedm.2016.7838394
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A new ruler on the storage market: 3D-NAND flash for high-density memory and its technology evolutions and challenges on the future

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Cited by 41 publications
(18 citation statements)
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“…The revolutionary move to 3D memories was not without problems, as discussed in [29]. In fact, while traditional device reliability issues must still be accounted for, new phenomena came to prominence, which are not merely an extension of what has already been observed on planar devices, but rather a consequence of the different device and array fabrication.…”
Section: Introductionmentioning
confidence: 97%
“…The revolutionary move to 3D memories was not without problems, as discussed in [29]. In fact, while traditional device reliability issues must still be accounted for, new phenomena came to prominence, which are not merely an extension of what has already been observed on planar devices, but rather a consequence of the different device and array fabrication.…”
Section: Introductionmentioning
confidence: 97%
“…In the area scaling technology, three dimensional (3D)-NAND flash memory has replaced conventional planar NAND devices owing to smaller size of NAND flash memory devices [1]. A high aspect ratio etching process and multiple dielectric deposition for charge trapping and isolation are required to perform area scaling in 3D-NAND flash memory; this increases the complexity of device manufacturing.…”
Section: Introductionmentioning
confidence: 99%
“…Three dimensional (3D) NAND architecture has become mainstream in NAND flash memory markets, producing better reliability, bit-density, and cost effectiveness than comparable technologies [1]- [3]. Manufacturers are massproducing 3D NAND flash memories through bit-cost scalable (BiCS) and terabit cell array transistor (TCAT) technologies [2], [3].…”
Section: Introductionmentioning
confidence: 99%
“…In this respect, 3D NAND technologies utilizing vertically stacked memory cells, to increase bit density, were more vulnerable to stress issues [5]- [7]. Specifically, the increased metal gate volume greatly influences the residual stress in the device by contributing to wafer bending, which therefore degrades the uniform depth of focus (DOF) required in the lithography process [1], [6], [7]. In additions, residual stress also enhances the non-uniformity in physical parameters, which is one of the causes of deterioration of device performance and reliability [4], [8].…”
Section: Introductionmentioning
confidence: 99%