A new realization scheme for dynamic PFSCL style

Sivaram, Ranjana; Gupta, Kirti; Pandey, Neeta

doi:10.1016/j.vlsi.2020.05.004

Cited by 3 publications

(3 citation statements)

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“…In this paper, an alternative to SCL circuit design methodology is presented which can be named as Active Loaded Source Coupled Logic (ALSCL) family of gates. In the proposed design scheme, the logic swings are close to V DD and GND levels of the supply voltages, and noise margins are much larger compared to the other single-ended source coupled topologies such as positive-feedback source coupled logic circuits [14][15][16]. Moreover, the proposed logic circuit style can be interfaced with static CMOS logic circuits without requiring any level restoration logic.…”

Section: Introductionmentioning

confidence: 97%

“…In the proposed design scheme, any of the NAND, NOR, XOR structures can be built effectively. On the other hand, PSCL scheme in [14,15] and others, the logic gates can only be built using NOR gates using De'Morgan's conversions, which results more number of gate requirement for the realization of logic functions.…”

Section: Introductionmentioning

confidence: 99%

“…Although the SCL have many advantages, there are also some of design difficulties, such as, complicated routing structure, higher current consumption when switching activity of the logic cell is low etc. For simpler design methodology, also single-ended source coupled logic circuits are proposed [14][15][16][17][18]. However, single-ended SCL circuits also suffer from lower noise margins [17].…”

Section: Introductionmentioning

confidence: 99%

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Active Loaded Source Coupled Logic: Circuit Design Techniques and Delay Modeling

Cini

Wang

2022

Preprint

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In this paper, a single-ended source coupled logic family is introduced, based on active loaded differential pair as the core element. The circuit style is a member in the source-coupled logic family with single-ended output structure whereas conventional source-coupled circuit topology is fully differential. The proposed circuit style does not suffer from low noise margins and complicated routing structure, compared to other source coupled logic design techniques. The proposed logic family has advantages such as simple design methodology, analog friendly nature and better compatibility to electronic design automation tools when source coupled design is considered. In the paper, gates for the proposed logic family is developed and a delay-model is given for the initial calculations. To show the functionality and robustness of the structures, various SPICE circuit simulations are done for different technology nodes as 0.35μm and 0.18μm. The results show that the proposed circuit structure provides superior topological properties compared to the other single-ended source coupled logic design styles. The proposed logic family may be an advantageous logic design alternative especially for mixed-signal designs where low noise and analog-friendly design is desirable.

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Section: Introductionmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%