Active Loaded Source Coupled Logic: Circuit Design Techniques and Delay Modeling

Abstract

In this paper, a single-ended source coupled logic family is introduced, based on active loaded differential pair as the core element. The circuit style is a member in the source-coupled logic family with single-ended output structure whereas conventional source-coupled circuit topology is fully differential. The proposed circuit style does not suffer from low noise margins and complicated routing structure, compared to other source coupled logic design techniques. The proposed logic family has advantages such as simple design methodology, analog friendly nature and better compatibility to electronic design automation tools when source coupled design is considered. In the paper, gates for the proposed logic family is developed and a delay-model is given for the initial calculations. To show the functionality and robustness of the structures, various SPICE circuit simulations are done for different technology nodes as 0.35μm and 0.18μm. The results show that the proposed circuit structure provides superior topological properties compared to the other single-ended source coupled logic design styles. The proposed logic family may be an advantageous logic design alternative especially for mixed-signal designs where low noise and analog-friendly design is desirable.