A New Paradigm for Low-power, Variation-Tolerant Circuit Synthesis Using Critical Path Isolation

Abstract

Design considerations for robustness with respect to variations and low power operations typically impose contradictory design requirements. Low power design techniques such as voltage scaling, dual-Vth etc. can have a large negative impact on parametric yield. In this paper, we propose a novel paradigm for low-power variationtolerant circuit design, which allows aggressive voltage scaling. The principal idea is to (a) isolate and predict the set ofpossible paths that may become critical under process variations, (b) ensure that they are activated rarely, and (c) avoid possible delay failures in the critical paths by dynamically switching to two-cycle operation (assuming all standard operations are single cycle), when they are activated. This allows us to operate the circuit at reduced supply voltage while achieving the required yield. Simulation results on a set of benchmark circuits at 70nm process technology show average power reduction of 60% with less than 10% performance overhead and 18% overhead in die-area compared to conventional synthesis. Application of the proposed methodology to pipelined design is also investigated.

Variable latency VLSI design based on timing analysis, delay ATPG, and completion prediction

“…For simplicity, we target only average performance for now, while this problem formulation can be easily modified to target other design objectives such as low power as in CRISTA [4], [5].…”

“…A variable-latency adder may include a fast and incomplete adder including only carry chains of a length no more than k (Figure 1), and a slow and complete adder, with a predictor selecting one of the two adders [9]. This variable-latency logic design technique can be extended to other arithmetic units such as multipliers [10], and random logic blocks [4], [5].…”

“…In a variable-latency design, logic computation in a stage is allowed to complete in more than one clock cycles, that is achieved by a completion prediction unit that predicts the computation latency and triggers a clock gating scheme for any extra clock cycles [7], [9], [4], [5]. The flexibility provides new room for performance improvement and power consumption reduction.…”

Variability-aware duty cycle scheduling in long running embedded sensing systems

“…RELATED WORK Prior work that addresses variability can be classified into (i) statistical design approaches [25] [9] [17], (ii) post silicon compensation and correction [12] [18] [32], and (iii) variation avoidance [8] [3] [11]. Our work differs in that it addresses hardware variability in the operating system layer.…”

Guided Probabilistic Checksums for Error Control in Low Power Digital-Filters

“…The method presented in [8] allows reduction of voltage margins by dynamic supply voltage control and monitoring of the circuit error rate. It is observed that even when the circuit logic delay is marginally longer than the critical path delay of the circuit (due to supply voltage reduction), the resulting logic error rate increases marginally due to the fact that the circuit critical paths are excited infrequently by the applied stimulus [9]. As the supply voltage is decreased further, this error rate increases rapidly leading to a large deterioration in output signal quality.…”