Variability-aware duty cycle scheduling in long running embedded sensing systems

Wanner, Lucas; Balani, Rahul; Zahedi, Sadaf; Apte, Charwak; Gupta, Puneet; Srivastava, Mani

doi:10.1109/date.2011.5763031

Cited by 11 publications

(6 citation statements)

References 41 publications

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“…Most efforts dealing with variation have focused on mitigating and exploiting it in processors [6], [7], [11], [12] or in on-chip memory [13], [14], [15], [16], [17]. Fewer papers have looked at variability in off-chip, DRAM-based memory subsystems.…”

Section: Related Workmentioning

confidence: 99%

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings

Gottscho

Bathen

Dutt

et al. 2015

IEEE Trans. Comput.

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Abstract-Hardware variability is predicted to increase dramatically over the coming years as a consequence of continued technology scaling. In this paper, we apply the Underdesigned and Opportunistic Computing (UnO) paradigm by exposing system-level power variability to software to improve energy efficiency. We present ViPZonE, a memory management solution in conjunction with application annotations that opportunistically performs memory allocations to reduce DRAM energy. ViPZonE's components consist of a physical address space with DIMM-aware zones, a modified page allocation routine, and a new virtual memory system call for dynamic allocations from userspace. We implemented ViPZonE in the Linux kernel with GLIBC API support, running on a real x86-64 testbed with significant access power variation in its DDR3 DIMMs. We demonstrate that on our testbed, ViPZonE can save up to 27.80 percent memory energy, with no more than 4.80 percent performance degradation across a set of PARSEC benchmarks tested with respect to the baseline Linux software. Furthermore, through a hypothetical "what-if" extension, we predict that in future non-volatile memory systems which consume almost no idle power, ViPZonE could yield even greater benefits, demonstrating the ability to exploit memory hardware variability through opportunistic software.

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Section: Related Workmentioning

confidence: 99%

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings

Gottscho

Bathen

Dutt

et al. 2015

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…3, where power (write, read, and idle) variability is shown across various categories (e.g., across all nineteen 1 GB DIMMs tested, across same exact parts, etc.) tested at 30 C. As a result, just like [62,51,46] exploited variability in processor power consumption, our goal is to adapt our memory management layer and opportunistically take advantage of these variations to reduce power consumption.…”

Section: Variations In the Memory Subsystemmentioning

confidence: 99%

Variability-aware memory management for nanoscale computing

Dutt

Gupta

Nicolau

et al. 2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-As the semiconductor industry continues to push the limits of sub-micron technology, the ITRS expects hardware (e.g., die-to-die, wafer-to-wafer, and chip-to-chip) variations to continue increasing over the next few decades. As a result, it is imperative for designers to build variation-aware software stacks that may adapt and opportunistically exploit said variations to increase system performance/responsiveness as well as minimize power consumption. The memory subsystem is one of the largest components in today's computing system, a main contributor to the overall power consumption of the system, and therefore one of the most vulnerable components to the effects of variations (e.g., power). This paper discusses the concept of variability-aware memory management for nanoscale computing systems. We show how to opportunistically exploit the hardware variations in onchip and off-chip memory at the system level through the deployment of variation-aware software stacks.

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“…The resulting Underdesigned and Opportunistic (UNO) computing machines can be classified along following two axes: (a) Type of Underdesign: use parametrically under-provisioned circuits (e.g., voltage overscaling as in [4], [5]) or be implemented with explicitly altered functional description (e.g., [3], [6]); and (b) Type of Operation: rely upon application's level of tolerance to limited errors (as in [7], [8]) to ensure continued operations. By contrast, error-free UNO machines correct all errors (e.g., [4]) or rely on hardware to correct-operation limits (e.g., [1], [2]). …”

Section: Figure 1 Itrs Projections Of Variabilitymentioning

confidence: 99%

Underdesigned and Opportunistic Computing

Gupta

2011

2011 Asian Test Symposium

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Abstract-Variation in the specifications of microelectronic chips across parts and over time has been a great source of concern for the integrated circuit chip designers because of the everincreasing guard-bands that the circuit and system designers must rely upon to ensure working parts and systems. This prompts us to look for solutions that can mitigate the effect of performance and power variability through innovations in system software. In this paper, we outline a novel, flexible hardwaresoftware stack and interface that use adaptation in software to relax variation-induced guard-bands in hardware design. 1

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Variability-aware duty cycle scheduling in long running embedded sensing systems

Cited by 11 publications

References 41 publications

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings

Variability-aware memory management for nanoscale computing

Underdesigned and Opportunistic Computing

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