A new multilevel inverter topology

Abstract

Multilevel converters are being considered for an increasing number of applications due to their high power capability, associated with lower output harmonics and lower commutation losses. Their main disadvantage is their complexity which requires both a great number of power devices an a rather complex control circutry. In this work a new inverter topology using an auxiliary switch is presented, reducing the number of power devices required to implement a multilevel output. The topology is tested in the design of a 5 levels H bridge simplified inverter; circuit operation is presented, simulated in SPICE and validated with experimental tests performed on a laboratory prototype. Additionally, the dedicated modulator circuit required for multilevel inverter operation is implemented using a FPGA circuit, reducing overall system cost and complexity.

Transistor clamped dual active bridgeDC‐DCconverter to reduce voltage and current stress in low voltage distribution network

“…Taking into account 5‐level inverter, employing five switches which was initially proposed in Reference 32, transistor clamped dual active bridge (TC‐DAB) converter is initially introduced in Reference 33. However, authors have presented only introduction and simulation results of proposed TC‐DAB converter.…”

Analysis, design and performance characterisation of transistor clamped dual active bridge DC–DC converter in wide voltage range

“…Taking into account five‐level inverter, employing five switches which was initially proposed in [28], transistor clamped dual active bridge (DAB) converter is proposed in this paper. Proposed converter has three degrees of freedom as compared to conventional two‐level DAB, which has only one degree of freedom to regulate power flow when controlled with SPS technique.…”

A Modified Switched-Diode Topology for Cascaded Multilevel Inverters

“…However, the symmetric topologies can produce a lower number of voltage levels in comparison with the asymmetric topologies. To have the same condition, the proposed topology in the symmetric mode P 1 is compared with the symmetric MLI topologies presented in [3], [5]- [6], [8], [13]- [14], [17]- [19], [22], [24] and with the symmetrical CHB [31]. The asymmetrical operation of the proposed multilevel inverter P 2 is also compared along with the asymmetrical operation of the topology in [22] represented as 'A' in Fig 4 (a)-(e).…”

“…They are also equipped with an H-Bridge for polarity reversal to synthesize an odd number of output voltage levels of either polarity. The Type I LS part consists of an Auxiliary (AUX) switch of a bidirectional nature, formed by a switch surrounded by four diodes [5], [6].…”