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Summary The provision of significant redundant states in multilevel inverters (MLIs) aids in fault‐tolerant operation. However, this deals with several components, leading to low reliability. This paper proposes a new fault‐tolerant five‐level MLI with reduced component count, which can withstand both single‐ and multiple‐switch faults. The reduced carrier‐based level shifted sinusoidal pulse width modulation (RCLSPWM) strategy is developed to generate control signals for the switches. The employed control scheme automatically balances the voltage across the capacitor. The logic gate expressions for generating gate pulses of the switches under normal and fault‐tolerant operating modes are described in detail. The comparative analysis is carried out to demonstrate the effectiveness of the proposed topology over other existing similar topologies. The performance of the laboratory prototype developed is found satisfactory as compared to other existing topologies under various operating conditions.

A high reliable inverter with photovoltaic systems improves the efficiency and longevity of the entire system. Recent research emphasises on developing new fault‐tolerant multilevel inverter (FTMLI) topologies. However, these topologies are not able to maintain rated voltage and power with a minimum switch count under switch fault conditions. This study proposes a new multilevel inverter with a reduced device count, which can handle both single switch fault and multi‐switch fault by preserving its rated voltage and power. Sine‐carrier‐based level‐shifted pulse‐width modulation is used to generate control signals. The carriers are reconfigured based on the type and location of the fault. The loss contribution of each switch is calculated in all modes of operation by considering variations in junction temperature using a Powersim (PSIM) thermal model tool. This study helps to choose an appropriate heat sink for the switches. The reliability density function is calculated using a Markov chain model. A comparative study is presented to assess the notable benefits of the proposed topology over other existing similar topologies. The experimental results from the laboratory prototype are provided to verify the efficacy and practicality of the proposed FTMLI configuration.

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