A New Mode of Operation for Arbiter PUF to Improve Uniqueness on FPGA

Abstract

Abstract-Arbiter-basedPhysically Unclonable Function (PUF) is one kind of the delay-based PUFs that use the time difference of two delay-line signals. One of the previous work suggests that Arbiter PUFs implemented on Xilinx Virtex-5 FPGAs generate responses with almost no difference, i.e. with low uniqueness. In order to overcome this problem, Double Arbiter PUF was proposed, which is based on a novel technique for generating responses with high uniqueness from duplicated Arbiter PUFs on FPGAs. It needs the same costs as 2-XOR Arbiter PUF that XORs outputs of two Arbiter PUFs. Double Arbiter PUF is different from 2-XOR Arbiter PUF in terms of mode of operation for Arbiter PUF: the wire assignment between an arbiter and output signals from the final selectors located just before the arbiter. In this paper, we evaluate these PUFs as for uniqueness, randomness, and steadiness. We consider finding a new mode of operation for Arbiter PUF that can be realized on FPGA. In order to improve the uniqueness of responses, we propose 3-1 Double Arbiter PUF that has another duplicated Arbiter PUF, i.e. having 3 Arbiter PUFs and output 1-bit response. We compare 3-1 Double Arbiter PUF to 3-XOR Arbiter PUF according to the uniqueness, randomness, and steadiness, and show the difference between these PUFs by considering the mode of operation for Arbiter PUF. From our experimental results, the uniqueness of responses from 3-1 Double Arbiter PUF is approximately 50%, which is better than that from 3-XOR Arbiter PUF. We show that we can improve the uniqueness by using a new mode of operation for Arbiter PUF.

An Arbiter PUF Secured by Remote Random Reconfigurations of an FPGA

“…Even though we are sure that the derived delay differences are correct, because they enable a correct prediction of responses, we did not achieve a deeper understanding of their distribution, e.g. of the surprisingly strong correlation of the delay values in consecutive stages 7 . The inter-chip differences in Fig.5 are mainly due to manufacturing variance.…”

“…An arbiter PUF [2,1,7] consists of a chain of N pairs of multiplexers (with an "upper" and "lower" multiplexer) through which pass two signals that started at the same time. Each multiplexer pair is controlled by one bit of a challenge of N bits.…”

“…Therefore we needed to test uniformity, uniqueness and reliability of our PUF with the finally chosen placement strategy that is described in Section 3.1. Uniformity was determined as the bias 9 of our construction displayed 7 We will argue below (Section 5) that the difficulty of understanding the routing enhances the security of our design by obfuscation. 8 Therefore our PUF construction has 0.0072 × 2 64 = 1.3 × 10 17 m-challenges.…”

Implementation of double arbiter PUF and its performance evaluation on FPGA

“…Our previous work also clarifies that the low-unique responses on Xilinx Virtex-5 FPGA is due to the difficulty of equallength wiring on Xilinx Virtex-5 FPGA [2]. Accordingly, we introduce a new APUF called DAPUF that enhances the uniqueness of APUF [1]. However, there exist no results for prediction attacks on DAPUF.…”

“…In the prediction attacks, an attacker tries to predict the responses from APUF by using a machine-learning model [5]. There- * Although this paper is based on [1,2], we evaluate a resistance against machine-learning attacks as shown in Table I. fore, in this paper, we aim at implementing a highuniqueness PUFs on FPGAs that has a high-tolerance against machine-learning attacks.…”