A New Methodology for Monitoring and Comparing Edge Exposure and Plasma Charging Current Damage from Plasma Processing

Abstract

We have recently demonstrated that gate-definition reactive ion etching (NE) of polycrystalline silicon (poly-Si) gate, 0.5 pm channel length MOSFET transistors can cause plasma exposure edge damage El] in addition to the well-known plasma charging current damage. Here we focus more closely on this gate edge damage and show, for the first time, that it manifests itself as distinct trapping and detrapping localized states at or near the SiOgsubstrate Si interface in the thin gate oxide around the gate perimeter. In this study we used devices of the type shown in Fig. l(a) with the gate edge over field oxide(which we term field devices) or in Fig. 2(a) with the gate edge over gate oxide (which we term gate devices). Both types of devices were fabricated on 8 in., p-type epitaxial Si wafers with poly-Si over 70A gate oxide active regions that were defined using the LOCOS technique. The gate devices had two variations : one with the same perimeter as the field device and the other, referred to hereafter as comb-structure gate device, with 25 times the perimeter of the field device. All gate and field devices had the same active area. We note that the field device represents the situation in a transistor during gate definition etch up to the overetch ; i. e., any plasma damage must be due to the flow of plasma charging currents. The gate devices, however, represent the situation in a transistor afier the main and overetch ; i. e., the gate oxide at the gate edge has now been exposed to the particle and photon bombardment of the plasma. To compare etch damage in these structures a simple, twoterminal characterization approach using cyclic voltage-sweep current-voltage (IV) measurements was undertaken in the pre-Fowler-Nordheim voltage regime. More precisely, I was measured at some adjustable time Atd after a step dV/dt (t is time) in the sweep. Sweeping-induced charging current peaks were found as seen in Figs. l@) and 2@) for a field device and a gate device, respectively. These peaks represent trapping and detrapping charging currents siice their sign depends on the sense of dV/dt. The fact that some of the trapping and detrapping states seen in Fig. 2b are located at the device edge is very evident from our comb-structure gate devices where the forward charging peaks were found to be more than 20 times those seen in the field devices. These trapping/detrapping current peaks essentially disappear in field devices and are diminished in gate devices upon white light illumination (Figs. l(c) and 2(c)). This suggests that the localized states giving rise to the peaks communicate with the Si substrate and, in the presence of photogenerated carriers, they are able to charge and discharge within the measurement time Atd. Differences in these trappinddetrapping states in field devices and gate devices are apparent with annealing and Fowler-Nordheim (FN) stress. The differences seen with annealing at 400 "C in forming gas (6% H2 and 94% N2) for 30 minutes are presented in Figs. l(d) and 2(d). The states in the field device a...