A new methodology for accurate predictive robustness analysis of designs implemented in SRAM-based FPGAs

Leveugle, Régis; Jrad, M. Ben

doi:10.1109/icecs.2010.5724726

Cited by 5 publications

(4 citation statements)

References 13 publications

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“…Because the faults induced by FIAs can be modeled at the logic level, several hardware-based emulation methods for FIAs are proposed. FPGA-based fault injection emulation techniques can be classified into reconfiguration-based [13,25,37] and instrumentation-based [19,39,40] techniques. Reconfiguration-based techniques rely on the mechanism of dynamic reconfiguration of FPGAs and modification of bitstreams to inject faults.…”

Section: Fpga-based Fault Injection Emulation Techniquesmentioning

confidence: 99%

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Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs

LiuQiang

TangHonghui

ZhangPeiran

2021

ACM Trans. Des. Autom. Electron. Syst.

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Fault injection attack (FIA) has become a serious threat to the confidentiality and fault tolerance of integrated circuits (ICs). Circuit designers need an effective method to evaluate the countermeasures of the IC designs against the FIAs at the design stage. To address the need, this article, based on FPGA emulation, proposes an in-circuit early evaluation framework, in which FIAs are emulated with parameterized fault models. To mimic FIAs, an efficient scan approach is proposed to inject faults at any time at any circuit nodes, while both the time and area overhead of fault injection are reduced. After the circuit design under test (CUT) is submitted to the framework, the scan chains insertion, fault generation, and fault injection are executed automatically, and the evaluation result of the CUT is generated, making the evaluation a transparent process to the designers. Based on the framework, the confidentiality and fault-tolerance evaluations are demonstrated with an information-based evaluation approach. Experiment results on a set of ISCAS89 benchmark circuits show that on average, our approach reduces the area overhead by 41.08% compared with the full scan approach and by over 20.00% compared with existing approaches. The confidentiality evaluation experiments on AES-128 and DES-56 and the fault-tolerance evaluation experiments on two CNN circuits, a RISC-V core, a Cordic core, and the float point arithmetic units show the effectiveness of the proposed framework.

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Section: Fpga-based Fault Injection Emulation Techniquesmentioning

confidence: 99%

“…Several approaches have been proposed to simulate or emulate FIAs in the literature, including software-based simulation [35] and hardware-based emulation [13,19,25,33,37,40]. Softwarebased simulation fully utilizes the flexibility and observability of software to imitate malfunctions of designs.…”

Section: Introductionmentioning

confidence: 99%

Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs

LiuQiang

TangHonghui

ZhangPeiran

2021

ACM Trans. Des. Autom. Electron. Syst.

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“…Emulation-based fault injections have been performed for some benchmarks with the environment presented in [23] to validate the level of protection. Some results are shown in Table III.…”

Section: Protection Efficiencymentioning

confidence: 99%

On improving at no cost the quality of products built with SRAM-based FPGAs

Leveugle

Jrad

2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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Product or design quality encompasses many aspects. One of them is the robustness with respect to perturbations. This robustness depends on the implementation technology, but can also be improved at design time. This paper is focused on designs implemented in SRAM-based FPGAs that are sensitive to soft errors in the configuration memory. An approach is proposed to increase the dependability with respect to configuration errors, at no cost, by selectively hardening parts of the design. The selection of locally duplicated functions is made so that the protections take advantage of FPGA resources that would not be used by the implemented design. An automated design flow is presented for Xilinx Virtex V devices and fault injection results show that the design dependability may be noticeably enhanced. As an example, more than 40% of the LUTs used to implement a Leon3 Sparc v8 processor can be protected against multiple configuration errors with less than 20% resource overheads at the block level. The final system-level overhead may in many cases be null for a given product, either due to the discrete sizes of available FPGAs or to a different repartition of resource budget between system blocks.

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“…We proposed in [10] an approach based on the injection of more realistic error patterns. We recall here the main principles to achieve self-contained contents of this paper.…”

Section: B Our Pattern-based Approachmentioning

confidence: 99%