A new method for measuring signal integrity in CMOS ICs

2010 Asia-Pacific International Symposium on Electromagnetic Compatibility

et al. 2010

This paper deals with the propagation of RF disturbances injected inside an integrated circuit. To increase our knowledge about this topic, an on-chip voltage sensor is implemented inside a test vehicle to quantify the conducted RF disturbances injected on the power supply of its I/Os. The experiment results give information about coupling paths taken by conducted disturbances carried into I/Os. I/O immunity thresholds computed from standard external immunity tests (IEC 62132-4) are compared to the one deduced from internal measurements. Moreover, in view of developing simulation tools for IC's immunity prediction, a test vehicle model is proposed. Comparison between simulation results, internal and external measurements raises some discussions about the accuracy of immunity measurement set-ups.

Section: B On-chip Samplingmentioning

confidence: 99%

On-chip sampling and EMC modeling of I/Os switching to evaluate conducted RF disturbances propagation

Deobarro¹,

Vrignon²,

2010 Asia-Pacific International Symposium on Electromagnetic Compatibility

et al. 2010

“…The proposed sensor was firstly designed, in the early 2000 [3], to accurately measure on chip noise in time domain to address signal and power integrity issues [15].…”

Section: Random Acquisition Principlementioning

confidence: 99%

IC Immunity Modeling Process Validation Using On-Chip Measurements

Boyer

Vrignon³

et al. 2012

J Electron Test

Developing integrated circuit (IC) immunity models and simulation flow has become one of the major concerns of ICs suppliers to predict whether a chip will pass susceptibility tests before fabrication and avoid redesign cost. This paper presents an IC immunity modeling process including the standard immunity test applied to a dedicated test chip. An on-chip voltage sensor is used to characterize the radio frequency interference propagation inside the chip and thus validate the immunity modeling process.

“…A first version of the on-chip noise sensor was designed in the early 2000s to address signal and power integrity issues at circuit level [9] [10]. The sensor is based on a sequential equivalent-time sampling [11].…”

Section: A Synchronous On-chip Noise Sensormentioning

confidence: 99%

Design of on-chip sensors to monitor electromagnetic activity in ICs: Towards on-line diagnosis and self-healing

2014 15th Latin American Test Workshop - LATW

Boyer

2014

With the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of non-compliance becomes critical for circuit designers. On-chip characterization of noise becomes necessary for model validation and design optimization to reduce redesign costs and time-to-market for IC manufacturers. This paper presents an on-chip noise sensor dedicated to the study of various aspects of electromagnetic compatibility at circuit level, such as power and signal integrity, substrate coupling, conducted emission and susceptibility to electromagnetic interferences. The different architectures of the sensor are presented as well as a demonstration of its measurement performance and benefits through many case studies. Applications of on-chip measurement may be extended towards online diagnosis and self-healing.Index Terms-Electromagnetic compatibility, signal and power integrity, integrated circuits, on-chip sensor.