A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs

Katyal, V.; Geiger, R.L.; Chen, Degang J.

doi:10.1109/apccas.2006.342249

Cited by 30 publications

(12 citation statements)

References 4 publications

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“…Conventional comparator is connected as a negative feedback opamp during auto-zero [9][10][11]. Thus the comparator needs compensation to avoid stability issue during autozeroing.…”

Section: Dynamic Comparator With Auto-zeroingmentioning

confidence: 99%

A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters

Foong

Tan

Zheng

2011

Analog Integr Circ Sig Process

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This letter presents the design of a window successive approximation (SAR) analog-to-digital converter (ADC) using an ultra-fast, offset-cancelled auto-zero comparator for digital DC-DC converters. It is designed in a standard CMOS 0.18 lm process. The ADC has a dynamic reference voltage range to reduce power consumption. The auto-zero scheme of the comparator is realized internally with a preamplifier stage and a latch stage. Post-layout simulation shows that the response time of the comparator from low-to-high and high-to-low is 3.78 ns and 2.47 ns, respectively. The resolution of the proposed window SAR ADC is 7.5 mV. The ADC is fabricated as part of a digital DC-DC converter integrated circuit and measurement results show that an average power consumption of 0.8 lW is achieved. The transient time of the DC-DC converter is within 150 ns for a load current change of 495 mA.

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“…Conventional comparator is connected as a negative feedback opamp during auto-zero [9][10][11]. Thus the comparator needs compensation to avoid stability issue during autozeroing.…”

Section: Dynamic Comparator With Auto-zeroingmentioning

confidence: 99%

A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters

Foong

Tan

Zheng

2011

Analog Integr Circ Sig Process

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“…5 [9]. The comparator consists of two cross coupled differential pairs with inverter latch at the top.…”

Section: The Dynamic Comparatormentioning

confidence: 99%

A 2.4pJ/bit ASK demodulator with 100% modulation rate for 13.56MHz NFC/RFID applications

Cai

Pun

Kwong

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper, an Amplitude Shift Keying (ASK) demodulator circuit for Near Field Communication (NFC) target mode or Radio Frequency Identification (RFID) tag is designed by using sample and hold method. It features envelope detector, switch capacitor filter, dynamic comparator, clock extractor and phase generator. This demodulator was demonstrated and simulated in TSMC 0.18um CMOS technology with an average power of 32uW power consumption at 13.56Mbps Non-Return-to-Zero (NRZ) date rate for a carrier frequency of 13.56MHz. The minimum input voltage swing is 200mVpp.

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“…Therefore, it can be derived that offset voltage from mismatch can be approximated in the expression (12) where (13) (14) (15) (16) In BSIM3 and BSIM4 model, mobility and threshold voltage have a weak correlation in high-order terms [15], [16]. To simplify the derivation, we assume that and are uncorrelated with each other and have a nearly Gaussian distribution.…”

Section: A Static Offset Voltage From C and Mismatchesmentioning

confidence: 99%

“…Although the feature size of transistors continues to be scaled down, the associated parasitic capacitance is not necessarily decreased due to the reduction of the oxide thickness and the junction depths [5]. In [12], [13] , the authors point out that 1-fF or 2-fF capacitance mismatch at the output can lead to offset of several tens of millivolts. Comparing with the absolute capacitance mismatch, our study finds that the relative capacitance mismatch defined as will more significantly affect input offset voltage.…”

Section: Introductionmentioning

confidence: 96%

Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators

Zhan

Chen

et al. 2009

IEEE Trans. Circuits Syst. I

145

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When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the model: 1) static offset voltages from the mismatch in C ox and threshold voltage V th and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-m and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of "Lewis-Gray" structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.Index Terms-Dynamic comparators, dynamic offset voltage, Monte Carlo method, static offset voltage.

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A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs

Cited by 30 publications

References 4 publications

A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters

A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters

A 2.4pJ/bit ASK demodulator with 100% modulation rate for 13.56MHz NFC/RFID applications

Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators

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