A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters

Foong, Huey Chian; Tan, Margaret; Zheng, Yuanjin

doi:10.1007/s10470-011-9702-x

Cited by 2 publications

(2 citation statements)

References 10 publications

(10 reference statements)

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“…For example, self-calibration techniques compatible with CMOS process have been studied in [15][16][17][18][19]; in [20][21][22], crystal with replaced by high precision resistors, and integrated oscillator successfully achieves~50 ppm clock stability. However in those efforts, it either requires IC-incompatible RC components, or needs very-complex phase locking mechanism.…”

Section: Introductionmentioning

confidence: 99%

A 16 MHz, 59.2 ppm/°C CMOS DLL-Assisted VCO with Improved Frequency Stability Towards Single Chip Wireless IOT

Cao

Liu

et al. 2016

Mobile Netw Appl

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A 16 MHz, highly stable voltage controlled oscillator (VCO) is reported in this paper. The proposed VCO consists of three cross-coupled RC stages, and is fully compatible with standard CMOS process. A positively biased PN junction with negative temperature coefficient is incorporated in the design to compensate frequency drift. In addition, a delay locked loop (DLL) directly following the VCO is utilized to further improve the output stability caused by temperature variations. The designed circuit was implemented using CMOS 0.18 μm technology, and was validated through experiments. Measurement results show that the DLL-assisted VCO output variation across the 25~120°C temperature range is less than 0.56 %, corresponding to 59.2 ppm/°C. It also shows that the output standard deviation of the DLL-assisted VCO is only 6.816 KHz,~16.6 % better compared with the same VCO without DLL's assistance.

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Section: Introductionmentioning

confidence: 99%

A 16 MHz, 59.2 ppm/°C CMOS DLL-Assisted VCO with Improved Frequency Stability Towards Single Chip Wireless IOT

Cao

Liu

et al. 2016

Mobile Netw Appl

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“…An SAR ADC with two contiguous reference voltages is used in [8] to cover only a narrow input range. But this approach allows no change of set-point or window size.…”

Section: Introductionmentioning

confidence: 99%

A 10 bit 16-to-26 MS/s flexible window SAR ADC for digitally controlled DC–DC converters in 28 nm CMOS

Haenzsche

Höppner

Schüffny

2015

Analog Integr Circ Sig Process

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This paper presents a 10 bit charge redistribution successive approximation analog-to-digital converter (ADC) for integrated digitally controlled DC-DC converters. A timing efficient implementation of a window function is proposed, where only a reduced input range is converted. A redundant search is applied to overcome the speed limitation of the analog components. The window mode enables further speed enhancement without an increase of clock frequency and power consumption. Position of the set-point and size of the window is digitally adjustable every conversion. Fabricated in 28 nm low-power CMOS technology the ADC occupies only 110 9 85 lm 2 . In full range mode a conversion rate of 16 MS/s is achieved and in window mode 26.7 MS/s, respectively. With a measured total power consumption of 710 lW and 9.1 bit ENOB a FOM of 81 fJ/conv-step is reached. A large input range with constant resolution, highly linear characteristic, and high robustness to PVT variations together make this ADC an advantageous alternative to delay line or ring oscillator based window ADCs. The highly digital nature of the proposed architecture allows implementation in modern sub-100 nm CMOS technologies.

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A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters

Cited by 2 publications

References 10 publications

A 16 MHz, 59.2 ppm/°C CMOS DLL-Assisted VCO with Improved Frequency Stability Towards Single Chip Wireless IOT

A 16 MHz, 59.2 ppm/°C CMOS DLL-Assisted VCO with Improved Frequency Stability Towards Single Chip Wireless IOT

A 10 bit 16-to-26 MS/s flexible window SAR ADC for digitally controlled DC–DC converters in 28 nm CMOS

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