A new FPGA-based postprocessor architecture for channel mismatch correction of time interleaved ADCS

Abbaszadeh, Asgar; Dabbagh-Sadeghipour, Khosrov

doi:10.1109/sips.2009.5336252

Cited by 3 publications

(1 citation statement)

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“…Due to this, background calibration methods have been introduced in recent years to correct the mismatch effects. The effects from offset and gain mismatches can be easily removed by a simple least mean square (LMS) loop [7,8]. On the contrary, the aperture time error introduces a significant effect on the output signal spectrum: it depends on the input signal frequency [9].…”

Section: Introductionmentioning

confidence: 99%

Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC

Abbaszadeh

Aghdam

Muñoz

2019

Analog Integr Circ Sig Process

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Sample time error can degrade the performance of time-interleaved analog to digital converters (TIADCs). A fully digital background algorithm is presented in this paper to estimate and correct the timing mismatch errors between four interleaved channels, together with its hardware implementation. The proposed algorithm provides low computation burden and high performance. It is based on the simplified representation of the coefficients of the Lagrange interpolator. Simulation results show that it can suppress error tones in all of the Nyquist band. Results show that, for a four-channel TIADC with 10-bit resolution, the proposed algorithm improves the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 19.27 dB and 35.2 dB, respectively. This analysis was done for an input signal frequency of 0:09f s. In the case of an input signal frequency of 0:45f s , an improvement by 33.06 dB and 43.14 dB is respectively achieved in SNDR and SFDR. In addition to the simulation, the algorithm was implemented in hardware for real-time evaluation. The low computational burden of the algorithm allowed an FPGA implementation with a low logic resource usage and a high system clock speed (926.95 MHz for four channel algorithm implementation). Thus, the proposed architecture can be used as a post-processing algorithm in host processors for data acquisition systems to improve the performance of TIADC.

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Section: Introductionmentioning

confidence: 99%