A new FFT concept for efficient VLSI implementation: Part I - Butterfly processing element

Jaber, Marwan A.; Massicotte, Daniel

doi:10.1109/icdsp.2009.5201181

Cited by 13 publications

(5 citation statements)

References 11 publications

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“…The first and second stage sf the 1024 Point FFT processor is modeled in Verilog with RTL diagram as shown in Fig 9.then that processor operated in the cadence 45 nm technology to perform with high speed compared previous methods in [16], [17] The proposed SMSS based FFT/IFFT processor using Shared multiplier is designed using Xilinx ISE14.2 tool and modeled in Verilog HDL. The proposed FFT processors use shared multiplier to improve computation speed.…”

Section: Resultsmentioning

confidence: 99%

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A Shared Multiplier for Effectual Area of 1024 Point Fast Fourier Transform Processor

Sandhya¹

2017

IJRASET

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[15] are a high throughput and used multiple data paths to maintain easy synchronization control. The radix -4 MDC architectures improve the area by reducing of complex multipliers from three to one in each stage. To perform twiddle factor multiplications in one stage leads one clock cycle, another multiplication needs one more clock cycle faster than the system [13]. Therefore, the architecture in [13] may not use as high speed applications. To get high throughput rate, FFT architectures using folding transformations [14], [15] have proposed. For high speed applications, processors requires a through put rate of over 2 GS/s,radix-8or radix-16 algorithms are used [18].Normally, the FFT size is a power of two, for typical like 128 ,256 ,512 and 1024 FFT sizes are not powers of eight. That is radx-8 algorithms cannot handle these FFT sizes. To provide these requirements, the proposed 1024 FFT processor meets the OFDM requirements by using mixed Radix algorithm. Therefore the proposed processors can perform FFT computations for sizes of not powers of eight. A brief interpretation on the128/256,256/512-point MRMDC pipelined FFT processors [17], [18] with eight parallel data paths can operate on high clock frequency. To maintain the demands of OFDM systems, three types MRMDC architectures are proposed [17]. shared multiplier of 1024 -point eight parallel MRMDC FFT processor have Type 1 reduces the number of butterflying units(BU's in the first stage. Type 2 proposes the shared multiplier of 1024 processor can reduce the complex multipliers for radix-8 BU's in the second stage. Type 3 combines both the Type 1 and Type 2 can reduce the number of BU's and complex multipliers. Document and are identified in italic type, within parentheses, following the example. Some components, such as multi-leveled equations, graphics, and tables are not prescribed, although the various table text styles are provided. The formatter will need to create these components, incorporating the applicable criteria that follow.

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Section: Resultsmentioning

confidence: 99%

“…The radix-8 BU operates in the third stage using the input sequence from the second stage based on (4). In the existing architecture, the second stage consists of the radix-8 BU in [16] that requires 11 complex multipliers. The third stage using the radix-8 BU also requires 11 complex multipliers.…”

Section: Second and Third Stage Structurementioning

confidence: 99%

A Shared Multiplier for Effectual Area of 1024 Point Fast Fourier Transform Processor

Sandhya¹

2017

IJRASET

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“…The radix-2 2 T adder tree matrix in the FFT factorization process is defined as [1] and [14]- [21]:…”

Section: The Proposed Radix-2 3 Fftmentioning

confidence: 99%

An Efficient Data Parallelization of the Radix-2³ (Carbon) FFT on GPU/CPU

Jaber

Massicotte

Jaber

et al. 2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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Solving Complex Problem that is coupled with intensive workloads; necessities the access to a massively parallel computational power. Up to date, Graphic Processing Units (GPUs) are the only architecture that could handle the most complex computationally intensive workloads. In the light of this rapid-growing advancement in computational technologies, this paper will propose a high-performance parallel radix-2 3 FFT suitable for such GPU and CPU systems. The proposed algorithm could reduce the computational complexity by a factor that tends to reach pr if implemented in parallel (pr is the number of cores/threads) plus the combination phase to complete the required FFT.

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“…In modern digital signal processing system, Fast Fourier transform (FFT) algorithm has the irreplaceable status. Whether using filter to clear up the image noise, compressing image, or dealing with image recognition, FFT is always the necessary algorithm to realize the hardware structure [1]. In the requirement of real time performance, miniaturization and low power consumption, it is necessary to adopt the strategy which can reduce resources to realize the hardware design of FFT to fulfill all these requirements.…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Radix-r FFT Hardware Structure Design

Zhang

Zhao

2014

AMM

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A reconfigurable radix-r FFT structure design is proposed, to reduce the memory and time consumption caused by zero-paddling in traditional radix-2/4 methods. The radix-r FFT computing flow is divided into three iterative steps: rotate factors computation; memory access schedule; butterfly coefficients matrix multiplication. The hardware structure is depicted, in which the memory accessing schedule is implemented by a finite state machine, the rotate factors and butterfly coefficients are calculated by the Taylor series expansion. The time consumption of the proposed structure is analyzed, and with the arbitrary data points, an optimized radix can be used to minimize the computing time. Compared with traditional methods, the proposed design has the advantage of generality, less time consumption and hardware costs.

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A new FFT concept for efficient VLSI implementation: Part I - Butterfly processing element

Cited by 13 publications

References 11 publications

A Shared Multiplier for Effectual Area of 1024 Point Fast Fourier Transform Processor

A Shared Multiplier for Effectual Area of 1024 Point Fast Fourier Transform Processor

An Efficient Data Parallelization of the Radix-2³ (Carbon) FFT on GPU/CPU

A Reconfigurable Radix-r FFT Hardware Structure Design

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A new FFT concept for efficient VLSI implementation: Part I - Butterfly processing element

Cited by 13 publications

References 11 publications

A Shared Multiplier for Effectual Area of 1024 Point Fast Fourier Transform Processor

A Shared Multiplier for Effectual Area of 1024 Point Fast Fourier Transform Processor

An Efficient Data Parallelization of the Radix-23 (Carbon) FFT on GPU/CPU

A Reconfigurable Radix-r FFT Hardware Structure Design

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An Efficient Data Parallelization of the Radix-2³ (Carbon) FFT on GPU/CPU